The effort for verification and validation activities of safety critical embedded systems may consume up to 70% of the total development costs. Since automotive systems are rarely developed from scratch, but are based on existing systems that are modified, it is unfortunate that the impact of changes on the safety of the system cannot precisely be determined. Therefore, a re-verification of the...

Safety verification of real-time embedded systems is a complex and hot issue. This paper proposes a SysML/MARTE activity diagram (SMAD), which is extended from SysML activity diagram (SAD) with non-functional MARTE semantics, for the describing of the real-time embedded systems behaviors. To carry out the safety verification, we transform the SMAD into timed automata. The processes of the model...

Verification and validation (V&V) are the primary means to assess accuracy and reliability of computational simulations. V&V methods and procedures have fundamentally improved the credibility of simulations in several high-consequence application areas, such as, nuclear reactor safety, underground storage of nuclear waste, and safety of nuclear weapons. Although the terminology is not uniform a...

We desire a capability for the lifelong verification of complex embedded systems that degrade over time, such as a semi-autonomous car. The field of runtime verification has developed many tools for monitoring the safety of software systems in real time. However, these tools do not allow for uncertainty in the system’s state or failure, both of which are essential for monitoring hardware as it ...

Safety integrity level (SIL) verification is a critical step in safety lifecycle of safety-related systems (SRS). Introducing redundancy into SRS raises two issues: voting group configuration and common cause failures (CCF). In order to minimize CCF, diverse redundancy is widely adopted by SRS. However, in the past, almost all attention of SIL verification has been paid to identical redundancy,...

In this paper we deal with verification of safety properties of term-rewriting systems. The verification problem is translated to a purely logical problem of finding a finite countermodel for a first-order formula, which is further resolved by a generic finite model finding procedure. A finite countermodel produced during successful verification provides with a concise description of the system...

Safety-critical embedded systems go through rigorous verification processes before being put into service. Verification is a major source of cost in the development process because of the rigour with which the verification is carried out. Most designs are subject to high levels of change traffic during development. This greatly increases the cost of the development as the complete system may ne...

Efficient implementations of atomic objects such as concurrent stacks and queues are especially susceptible to programming errors, and necessitate automatic verification. Unfortunately their correctness criteria — linearizability with respect to given ADT specifications — are hard to verify. Even on classes of implementations where the usual temporal safety properties like control-state reachab...

A fundamental problem in the design and development of embedded control systems is the verification of safety requirements. Formal methods, offering a mathematical way to specify and analyze the behavior of a system, together with the related support tools can successfully be applied in the formal proof that a system is safe. However, the complexity of real systems is such that automated tools ...