In this paper the challenge of enhancing the gain and reducing the power requirement of amplifiers, preferably used in biomedical applications is addressed by demonstrating that composite cascode stages, operating in subthreshold/weak inversion regions provide a method of designing a ultra high gain (97dB) and low-power (21μW) op amp with 1.5V power supply. The op amp is designed without compen...

This paper describes a high-gain CMOS low-noise amplifier (LNA) for 2.4/5.2-GHz WLAN applications. The cascode LNA uses an inductor at the common-gate transistor to increase its transconductance equivalently, and therefore it enhances the gain effectively with no additional power consumption. The LNA is matched concurrently at the two frequency bands, and the input/output matching networks are ...

Power consumption is the major issue in VLSI design. In this paper an efficient low power first order sigma delta modulator is designed for oversampled ADC using floating gate folded cascode operational amplifier, in 0.35 μm Technology. Floating gate MOSFET have low power Dissipation hence it is an attractive solution in design of data converters, low voltage op -amp with rail-to-rail input and...

This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as the first stage and feature techniques such as common-mode stabilized active load, crosscoupled cascode connection, and close-loop pole placement. MOS switches are driven by bootstrapping circuits that do not subject t...

In this paper, feed-forward techniques are revised and used for the design of high-frequency Operational Transconductance Amplifiers (OTA). For the same power consumption and similar transistor dimensions the two-path and three-path folded-cascode OTAs present both smaller settling error and faster response as compared with the typical folded-cascode topology. Also, a No-Capacitor FeedForward (...

A two-stage self-biased cascode power amplifier in 0.18m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8–2.4-GHz frequen...

Problem statement: The Low Noise Amplifier (LNA) is a core block of an Ultra Wide Band (UWB) receiver since it amplifies a very weak signal received at the antenna to acceptable levels while introducing less self-generated noise and distortions. The LNA design poses a unique challenge as it requires simultaneous optimization of various performance parameters like power gain, input matching, noi...