With designing air pads on silicon-on-insulator (SOI) wafer periodically as a cellular structure, a 1×2 photonic band gap (PBG) beam splitter is proposed in this article . We study the characteristics of the designed 1×2 SOI PBG beam splitter and simulate the relationship of the two output power with the launching wavelengths. We use finite-difference-time-domain (FDTD) as simulation technique....

We investigate the influence of heteroepitaxially grown Ge on the thermal dewetting and agglomeration of the Si(0 0 1) template layer in ultrathin silicon-on-insulator (SOI). We show that increasing Ge coverage gradually destroys the long-range ordering of 3D nanocrystals along the 〈1 3 0〉 directions and the 3D nanocrystal shape anisotropy that are observed in the dewetting and agglomeration of...

An electroabsorption modulator using a side-entry architecture achieved a contrast ratio exceeding 3 dB over a 3.5 nm range in the C-band, using a voltage swing of 1 V and operating at 1008C. Modulation was due to the quantum-confined Stark effect from ten Ge/SiGe quantum wells epitaxially grown on silicon-on-insulator (SOI) wafers. The device exploits an asymmetric Fabry-Perot resonator formed...

Well-behaved Ge quantum well (QW) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) were fabricated on silicon-on-insulator (SOI) substrate. By optimizing the growth conditions, ultrathin fully strained Ge film was directly epitaxially grown on SOI at about 450 °C using ultra-high vacuum chemical vapor deposition. In situ Si2H6 passivation of Ge was utilized to form a high...

This paper reports a new approach to the fabrication of 3D structured diaphragms using integrated surface and deep reactive ion etching (DRIE) bulk silicon micromachining on a silicon-on-insulator (SOI) wafer. The fabrication process has been applied to a 1 mm × 2 mm × 1.2 μm diaphragm designed for a biomimetic directional microphone. The membrane has two 200 μm × 380 μm × 20 μm silicon proof m...

Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer. SOI wafers offer many advantages over conventional silicon wafers. In IC technology, the switching speed of circuits fabricated on SOI is increased by 20-50% co...

In this paper III-V on silicon-on-insulator (SOI) heterogeneous integration is reviewed for the realization of near infrared light sources on a silicon waveguide platform, suitable for inter-chip and intra-chip optical interconnects. Two bonding technologies are used to realize the III-V/SOI integration: one based on molecular wafer bonding and the other based on DVSBCB adhesive wafer bonding. ...

This paper describes applications of Silicon on Insulator (SOI) technology to high performance onchip memories (e.g. SRAMs and register files etc.).The primary focuses are on the important and unique issues in SOI technology such as performance gain, history effect, power reduction, pulsewidth control and self-heating. The effects on the interconnect performance and reliability are also discuss...

This work presents a comparative study of the transcapacitances an asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs with different gate lengths. analysis was done by means two-dimensional numerical simulations. Simulated results show influence others on gate-to-gate capacitance for ASC SOI device GC device.

A novel SOI (Silicon-On-Insulator) pixel photo detector with full depletion and backgate surface potential pinning is proposed in this paper. The detector greatly increases charge-to-voltage conversion gain while stabilizing the operation of SOI circuits. Low noise and wide dynamic range operations are attained. A double doping technique increasing potential barrier to holes at the surface regi...