In this paper, we proposed a 2-D analytical model for electrical characteristics such as surface potential, electric field and drain current of Silicon-on-Insulator Tunnel Field Effect Transistor (SOI TFETs) with a SiO2/High-k stacked gate-oxide structure. By using superposition principle with suitable boundary conditions, the Poisson’s equation has been solved to model the channel r...

The three-dimensional (3D) integrated circuit technology developed by MIT Lincoln Laboratory allows circuit structure that forms on several silicon-on-insulator (SOI) substrates to be integrated into a 3D integrated circuit. This 3D technology gives the possibility of better thermal and noise management, more compact design, and so on. However, circuit design in the 3D technology has not been f...

−Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed. Index Terms−Reli...

Starting with a brief review on 0.1m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number f...

We numerically study silicon waveguides on silica showing that it is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI) material system. Thin waveguides, or fins, exhibit geometrically softened mechanical modes at gigahertz frequencies with phase velocities below the Rayleigh velocity in glass, eliminating acoustic radiation l...

Silicon-on-insulator technology offers solutions to the higher-performance and lower-power dilemma Digital Systems: New two-antenna handset technology improves CDMA network performance Tx/Rx: Making phase shifters affordable for widespread commercial electronically scanned antenna arrays Mixed Signal: High-speed digital and mixed-signal ICs using advanced indium phosphide heterojunction bipolar...

Introduction Silicon-on-Insulator is emerging as a very suitable technology to develop silicon-based photonic integrated circuits. This technology is 100% CMOS compatible, allowing the development of planar optical devices and making possible to achieve very large scale integration (VLSI). However, nonlinear effects in silicon are inefficient. Materials which have superior optical properties, s...

The silicon-on-insulator (SOI) CMOS technology has a number of advantages over the standard bulk CMOS technology, such as no latch-up effect, high speed and low power. The fully depleted SOI (FD-SOI) technology provided by OKI Electric Industry Co., Ltd. is realizing the full features of the advantages with lowest junction capacitance. Test element group (TEG) structures of transistors were fab...

A low-power 435-MHz single-ended low-noise amplifier was implemented in a 0.35-μm silicon on insulator (SOI) CMOS technology. The SOI CMOS LNA has a simulated noise figure of 0.6 dB, input 1-dB compression point of –12.5 dBm, input thirdorder intercept point of –5 dBm, and small-signal gain of 22 dB. Total power dissipation is 10 mW from a 2.5-V supply. LNA chip area is 1.4 mm x 0.58 mm. Due to...