In this work a comparison between plasma-induced defects by two different SF6 texturing techniques, reactive ion etching (RIE) and high-density plasma (HDP) is presented. It is found that without any defect-removal etching (DRE), the minority carrier lifetime is the highest for the HDP technique. After DRE, the minority carrier lifetime rises as high as 750 ms for both RIEand HDP-textured wafer...

This paper reports a novel method to produce high density feedthrough glass wafers with sufficient thickness for the packaging and interconnection of high density array micro electromechanical systems (MEMSs). Pyrex glass wafers with thin film metal lines on the surface are stacked and bonded with each other using phenyl methyl siloxane-based adhesive. The stacked glass wafer block is then slic...

rapid thermal processing (rtp) has become a key technology for semiconductor device manufacturing in a variety of applications, such as thermal oxidation, annealing, and thin-film growth. hence, understanding the radiative properties of silicon and other relevant materials is essential for the analysis of the thermal transport processes. we have analyzed and calculated the spectral, directional...

Several techniques for fabrication of nanochannels on both glass and silicon substrates have been investigated. The techniques investigated here include glass to glass anodic bonding with an intermediate layer of amorphous silicon, silicon to silicon anodic bonding with an intermediate layer of glass, and AuAu thermo-compression bonding of silicon wafers. In each case, the conduit’s height is d...

A Introduction Research and manufacturing related to silicon devices, circuits, and systems often relies on the wet-chemical etching of silicon wafers. The dissolution of silicon using liquid solutions is needed for deep etching and micromachining, shaping, and cleaning. Also, wet-chemistries are often used for defect delineation in single crystal silicon materials. In this paper, a review of t...

The particle flow approach requires calorimeters with ultra-high granularity. The design of the Si/W ECAL has thus been based on this principle. It is composed of 30 layers, each layer having an array of 3 × 3 silicon matrices. These matrices or wafers are divided into 6 × 6 cells with an area of 1 cm. The mechanical structure consists of tungsten plates wrapped in carbon fiber, creating 15 alv...

Silicon-on-insulator ~SOI! has proven to be a viable alternative to traditional bulk silicon for fabrication of complementary metal–oxide–semiconductor devices. However, a number of unusual phenomena with regards to diffusion and segregation of dopants in SOI have yet to be explained. In the present study, SOITEC wafers were thinned to 700 and 1600 Å using oxidation and etching. Ion implantatio...

We show elasto-capillary folding of silicon nitride objects with accurate folding angles between flaps of (70.6 ± 0.1)° and demonstrate the feasibility of such accurate micro-assembly with a final folding angle of 90°. The folding angle is defined by stop-programmable hinges that are fabricated starting from silicon molds employing accurate three-dimensional corner lithography. This nano-patter...

Here we present a facile technique for the large-scale production of few-layer graphene flakes. The as-sonicated, supernatant, and sediment of the graphene product were respectively sprayed onto different types of silicon wafers. It was found that all devices exhibited current rectification properties, and the supernatant graphene devices have the best performance. Schottky junctions formed bet...