Nanometer CMOS VLSI circuits are highly sensitive to soft errors, also known as single-event upsets (SEU) that induce current pulses at random times and at random locations in a digital circuit. Environmental causes of SEU include cosmic radiation and high-energy particles. Our neutron induced soft error rate (SER) estimation method propagates single event transient (SET) pulses through the aff...

Due to cosmic rays, electronic devices such as SRAM may undergo some dysfunctions such as single event upsets also called Soft errors. A crucial issue for aerospace applications is to be able to predict the Soft Error rate of a given device in a given environment. In this work, we present a predictive tool which deals with protons and heavy ions for space applications and with neutrons for atmo...

SRAM-based FPGAs are popular in the aerospace industry for their field programmability and low cost. However, they suffer from cosmic radiationinduced Single Event Upsets (SEUs). Triple Modular Redundancy (TMR) is a well-known technique to mitigate SEUs in FPGAs that is often used with another SEU mitigation technique known as configuration scrubbing. Traditional TMR provides protection against...

In many computer systems, the contents of memory are protected by an error detection and correction (EDAC) code. Bit-flips caused by single event upsets (SEUs) are a well-known problem in memory chips and EDAC codes have been an effective solution to this problem. These codes are usually implemented in hardware using extra memory bits and encoding-decoding circuitry. In systems where EDAC hardw...

The continuous exponential growth in transistors per chip as described by Moore’s law has spurred tremendous progress in the functionality and performance of semiconductor devices, particularly microprocessors. At the same time, each succeeding technology generation has introduced new obstacles to maintaining this growth rate. Transient faults caused by single-event upsets have emerged as a key...

The present work contains information about the design and implementation of a SRAM memory that is able to cope with SEU and SET produced by radiation. This paper shows how two different techniques could be implemented together to aim that target. The architecture of the memory is proposed, and details of the different blocks are given. Also a new method is developed and proposed for automatic ...

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devices necessitate evaluating the SEU mechanisms of FinFET circuit stability at low supply voltages dissipation, it is also necessary over a range of voltages. FinFET proton exponential low simulations show that the weak variation of supply voltage critical charge Index Terms particles, Neutrons, Heavy The Semiconductor Industry Association (SIA) roadmap has identified power dissipation as one...

As CMOS technology scaling pushes towards the reduction of length transistors, electronic circuits face numerous reliability issues, and in particular nodes D-latches at nano-scale confront multiple-node upset errors due to their operation harsh radiative environments. In this manuscript, a new high reliable D-latch which can tolerate quadruple-node upsets is presented. The design based on low-...