This paper addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection (CSCD). To support this, a fully-decoupled latch controller has been developed, which integrates with the current sensing circuitry. Different configurations in which the ...

2 ACKNOWLEDGMENTS I am grateful to many people who supported and encouraged me during the work leading to this master project. I would like to specially thank Prof. Y. Leblebici, the director of Microelectronic Systems Laboratory (LSM), for his extensive support during master study and guiding me to select worthwhile research topics for both semester and master projects. I am grateful to him an...

The growing demand for energy constrained applications and portable devices have created a dire need for ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold region minimize the energy per operation, thus providing a better platform for ...

In this talk we will consider various classes defined by small depth polynomial size circuits which contain threshold gates and parity gates. We will describe various inclusions between many classes defined in this way and also classes whose definitions rely upon spectral properties of Boolean functions.

A Threshold Circuit consists of an acyclic digraph of unbounded fanin, where each node computes a threshold function or its negation. This paper investigates the computational power of Threshold Circuits. A surprising relationship is uncovered between Threshold Circuits and another class of unbounded fanin circuits which are denoted Finite Field ZP (n) Circuits, where each node computes either ...

In this paper, a low leakage multi Vth level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using MTCMOS technique and sleepy keeper. Multi Threshold CMOS is an effective circuit level technique that improves the performance and design by utilizing both low and high threshold voltage transistors. Power dissipation has become an overriding concern fo...

In this paper, we consider an optimization problem on directed acyclic graphs which is motivated by a standard task in low power VLSI design. With each vertex v of a directed acyclic graph, we associate two delay values d0(v) ≤ d1(v) and two leakage values c0(v) ≥ c1(v). The objective is to choose one of the indices 0 or 1 for each vertex, such that in first instance the corresponding total del...

We prove that any language in ACC can be approximately computed by two-level circuits of size 2('Ogn)', with a symmetric-function gate at the top and only AND gates on the first level. This implies that any language in ACC can be recognized by depth-3 threshold circuits of size 2('"gn)'. This result gives the first nontrivial upper bound on the computing power of ACC circuits.

On Threshold Circuits for Parity Ramamohan Paturi and Michael E. Saks* Department of Computer Science and Engineering University of California, San Diego; La Jolla, Ca 92093 Motivated by the problem of understanding the limitations of neural networks for representing Boolean functions, we consider sizedepth trade-offs for threshold circuits that compute the parity function. We give an almost op...

We show that for any constant d, complex roots of degree d univariate rational (or Gaussian rational) polynomials—given by a list of coefficients in binary—can be computed to a given accuracy by a uniform TC algorithm (a uniform family of constant-depth polynomial-size threshold circuits). The basic idea is to compute the inverse function of the polynomial by a power series. We also discuss an ...