This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of ...

Aiming to address the growth and integration of renewable sources electronic loads, different types dc-dc topologies with specific features have been proposed, going from medium frequency isolated Modular Multilevel Converter Switched Capacitor Hybrid topologies. In this paper, a bidirectional based converter is presented, featuring transformerless structure, automatic total arm voltages clampi...

Low supply voltages in modern CMOS technologies are expected to reduce the maximum resolution of analog to digital converters in voltage mode operation. This paper outlines the functionality and possibilities of switched current (SI) circuit techniques in medium accuracy DS modulators. Starting with the presentation of different kinds of switched current cells, this paper gives an overview abou...

The first major concern in clocking an SCF is the clock's duty cycle. Deviation from the range specified by most manufacturers (40% to 60%) produces inadequate settling of the switched-capacitor element, which can cause signal distortion, inaccurate filter response, and signal attenuation. Most sources inherently produce the desired 50% duty cycle; if not, that performance can be ensured by des...

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