The systolic array architecture is one of the most popular choices for convolutional neural network hardware accelerators. biggest advantage its simple and efficient design principle. Without complicated control dataflow, accelerators with can calculate traditional convolution very efficiently. However, this also brings new challenges to array. When computing special types convolution, such as ...

Based on the systolic array approach, new designs of special-purpose devices for filtering, correlation, convolution, and discrete Fourier transform are proposed and discussed. It is argued that because of high degrees of simplicity, regularity and concurrency inherent to these designs, their VLSI implementation will be cost effective. Introduction LSI technology allows tens of thousands of dev...

In an earlier paper, a systolic algorithm/array was derived for recursive least squares (RLS) estimation, which achieves an O(n0) throughput rate with O(n2) parallelism. The resulting array is specifically tuned towards the RLS problem. Here, a different route is taken, by trying to implement the RLS problem on a systolic array, which is also useful for several other applications, such as, e.g....