We have developed an algorithm by which to enable conventional microprocessors to test their on-chip SRAM using their existing hardware and software resources. This test method utilizes a mixture of existing memory testing techniques, which cover all important memory faults. This i; achieved by writing a routine called BIST Program by which only uses the existing ROM and creates no additional h...

This paper presents an improved estimation technique for hybrid BIST test set generation. In a hybrid BIST approach the test set is assembled from pseudorandom and deterministic test patterns. The efficiency of the hybrid BIST approach is determined by the ratio of those test patterns in the final test set. Unfortunately, exact algorithms for finding the optimal test sets are computationally ve...

This paper proposes a histogram BIST scheme for ADC static testing. This scheme makes use of time decomposition technique and space decomposition technique. The traditional ADC BIST approach based on time decomposition technique can reduce the test hardware overhead, however it will typically produce large testing time. For a monotonic ADC, the output codes have an approximate proportional rela...

The way integrated technology is growing becomes very difficult to apply circuit testing using Automatic TEST Equipment of complex circuit for this BIST (Built In Self test) is the solution of complex IC. Here we are applying BIST for UART which is considering as a low speed, low cost data exchange between computer and peripherals. Hence this paper shows implementation of UART with BIST capabil...

The increasing growth of sub-micron technology has resulted in the difficulty of testing. Design and test engineers have left no choice but to accept new responsibilities that had been performed by group of technicians in the previous years. Design engineers who do not design systems with full testability had increased the possibility of product failures and missed market opportunities. BIST is...

A new inter-core BIST circuits for tri-state buffers: T-BIST mainly consists of simple circuits distributed in the relevant blocks. It can give an excellent test-coverage with a little additional hardware. Its configuration is not specified by each SoC structure, so, it is suitable for a general/reusable testable IP.

Modulo 2 ÿ 1 adders as fast as n-bit 2’s complement adders have been recently proposed in the open literature. This makes a Residue Number System (RNS) adder with channels based on the moduli 2, 2 ÿ 1, and any other of the form 2 ÿ 1, with k < n, faster than RNS adders based on other moduli. In this paper, we formally derive a parametric, with respect to the adder size, test set, for parallel t...

Application of built-in self-test circuitries allows to improve the testing quality and reliability of complex analog and mixed-signal IC. BIST-circuitry is integrated to original circuit for the purpose of test signal generation, measurement of output responses and decision-making about correctness of circuit under test functioning. The most part of BIST-circuitries for analog and mixed-signal...

Circular built-in self-test (BIST) is a “test per clock” scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion. However, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. Th...

Embedded memories consume an increasing portion of the die area in deep submicron systems-on-a-chip (SOCs). Manufacturing test of embedded memories is an essential step in the SOC production that screens out the defective chips and accelerates the transition from the yield learning phase to the volume production phase of a new manufacturing technology. Built-in self-test (BIST) is establishing ...