In this paper we investigate threshold based networks performing 2 1 addition using redundant binary operand representations. In particular we concern with establishing the networks with the smallest network depth assuming small weight and fan-in values. First we propose a depth-4 implementation and we show that the 2 1 addition can be computed by a threshold network with the size in the order ...

We present simulation mechanisms by which any network of threshold logic units with either symmetric or asymmetric interunit connections (i.e., a symmetric or asymmetric \Hoppeld net") can be simulated on a network of the same type, but without any a priori constraints on the order of updates of the units. Together with earlier constructions, the results show that the truly asynchronous network...

This paper investigates the relationship between a single-electron gate probability of failure and the random variations affecting its elements. The study focuses on digital logic gates and circuits. Two major implementations are considered: static complementary logic gates and threshold logic gates (TLG). In addition to implementation, the effect of the gate fan-in on the reliability is invest...

Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits, by operating the devices at low currents and low voltages[1,2,3,4].It is known that MOS devices and circuits especially CMOS circuits consume relatively low power[5,6] . But there seems to be a need t...

We have investigated circuit options to surpass the 1-V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different onand off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use—from 1.5 down to 0.5 V. Since ordinary pass-transistor...

In this paper we investigate single electron tunneling (SET) devices from the logic design perspective, using the SET tunnel junction’s ability to control the transport of individual electrons. More specifically, we focus on the implementation of a family of Boolean Single Electron Encoded Logic (SEEL) gates, in which the logic values 0 and 1 are encoded as a net charge of 0 or 1 electron charg...

Abstract: Scaling supply voltage of FinFET circuits is an efficient method to achieve low power dissipation. Superthreshold FinFET logic circuits can attain low power consumption with favorable performance, because FinFET devices operating on medium strong inversion regions can provide better drive strength than conventional CMOS transistors. The supply voltage of the super-threshold circuit is...

As single electron tunneling technology based threshold logic gate uses less no of tunnel junctions so it reduces the size of Boolean logic gate compare to single electron tunneling based logic gate and single electron transistor based logic gate. The design and simulation of a 4:1 multiplexer based on buffered threshold logic gate is presented in this paper. The logic operation is verified usi...

This paper presents a novel type of nanoarchitecture which is both device and circuit independent. The starting idea is that computations can be performed in three fundamentally different ways: entirely digital (using Boolean gates), entirely analog (using high precision analog circuits), or mixed (using both digital and low precision analog circuits). The boundaries between these are sometimes...