This paper introduces the concept of a superword processor, a style of computer-architecture design in which a traditional processor datapath is replicated in SIMD fashion, transforming each machine instruction into a SIMD equivalent. Superword techniques are appealing because they require minimal changes to an existing design, offer backward compatibility with an existing ISA, and offer large ...

We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a core, its design must be supplemented with on-chip co-processors to obtain a cost-effective system. Good performance is obtained through a uniform 64-bit 5 issue-slot VLIW design, supporting subword parallelism with a...

Processors having both low-power consumption and high-performance are more and more required in the portable systems market. Although it is easy to nd processors with one of these characteristics, it is harder to nd a processor having both of them at the same time. In this paper, we evaluate the possibility of designing a high-performance, low-consumption processor and investigate whether instr...

The architecture of the TriMedia CPU64 is based on the TM1000 DSPCPU. The original VLIW architecture has been extended with the concepts of vector processing and superoperations. The new vector operations and superoperations need to be supported by the compiler and simulator to make them accessible to application programmers. It was our intention to support these new features while remaining co...

The performance of statically scheduled VLIW processors is highly sensitive to the instruction scheduling performed by the compiler. In this work we identify a major deficiency in existing instruction scheduling for VLIW processors. Unlike most dynamically scheduled processors, a VLIW processor with no load-use hardware interlocks will completely stall upon a cache-miss of any of the operations...

We have developed a new-generation, general-purpose digital signal processor (DSP) core with low power dissipation for use in third-generation (3G) mobile terminals. The DSP core employs a 4-way VLIW (very long instruction word) approach, as well as a dual-multiply-accumulate (dual-MAC) architecture with good orthogonality. It is able to perform both video and speech codec for 3G wireless commu...

This paper investigates a possible architecture to a dynamically adaptable processor. In this architecture, the running application is profiled and dynamic traces of high frequently executed loops (hot paths) are detected. The proposed online profiling methodology is mainly hardware-based so that overhead can be reduced as much as possible. Studying the behavior of branch and jump instructions,...

Power is rapidly becoming one of the primary design constraints for modern processor design due to increased complexity and speed of the system. Cycle-accurate microarchitecture-level power simulators such as Wattch [1], SimplePower [2], and TE EST [3], have been developed and used extensively to validate power-efficient microarchitecture innovations, including clock gating [4], dynamically rec...

This communication analyses the birth of RISC and CISC architectures and their evolution over the past 20 years. It gives an overview of the competition between both to win the performance race, by adding new features, mainly from the opposite side and in the end converging into what is now known as Post-RISC era. The communication complements this issue by taking a brief look into novel VLIW p...

This paper surveys past research on instruction scheduling for exploiting more Instruction Level Parallelism (ILP). We focus on static instruction scheduling performed by compiler. The hardware platform for implementing such compiler techniques, i.e. VLIW is also reviewed. We also give comparison between the code scheduling done dynamically by out-of-order machines and that by compilers, along ...