The articles in this issue are divided into two groups: 1) the first group comprises selected from 40th IEEE VLSI Test Symposium 2022 and 2) second consists of general interest articles.

Using a recently proposed VLSI algorithm for 2-D discrete sine transform (DST) an efficient VLSI architecture is proposed. This VLSI architecture has a modular and regular hardware structure and can compute in parallel thus resulting in high speed performances. The proposed architecture has been obtained by mapping the VLSI algorithm into two linear systolic arrays and combining them into a sin...

In digital VLSI system the clock distribution network and flip flops are most power consuming components. The reduction of power consumption by clock distribution networks & flip flop makes the total VLSI system as low power VLSI system. In the earlier VLSI system design, different power consumption methods are followed to design the various flip-flops .The SABFF(sense amplifier based flip flop...

Our daily lives heavily depends on the social information infrastructure, which includes a huge numbers of VLSI chips. Various system failures are caused by physical faults in the circuits, human errors in design/fabrication/operation and malicious attacks. In this paper, the causes and countermeasures of failures of VLSI are summarized. The discussion leads a new direction of researches of des...

It is well-known that all Boolean functions of n variables can be computed by a logic circuit with o(2n/n) gates (Lupanov's theorem) and that there exist Boolean functions of n variables which require logic circuits of this size (Shannon's theorem). We present corresponding results for Boolean functions computed by VLSI circuits, using Thompson's model of a VLSI chip. We prove that all Boolean ...

In the 80s of last century, integrated injection logic (I2L) was widely used as an elementbase. Somewhat later, in development I2L, injection-field (IPL) appeared for constructionof VLSI. Both element bases are close degree integration on a chip. An increase inthe into VLSI can be achieved using self-displacement regions, which theintroduction impurities different types is carried out single bo...

A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of func...

A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. &#10The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of fu...