The authors present a multiplication algorithm for low power implementation of digital filters on CMOS based digital signal processing systems. The algorithm decomposes individual coefficients into two primitive sub-components. The decomposition, performed using a heuristic approach, divides a given coefficient such that a part is produced which can be implemented using a single shift operation...

Most Digital Signal Processors perform computations on integers, or fixed-point numbers, rather than floating-point numbers. In contrast, Digital Signal Processing algorithms are often designed with real numbers in mind and usually implemented in floating-point. Apart from finite wordlength effects that may appear during signal acquisition and intermediate computations, limits on the signal pre...

Polyphase IIR structures have recently proven themselves very attractive for very high performance filters that can be designed using very few coefficients. This, combined with their low sensitivity to coefficient quantization in comparison to standard FIR and IIR structures, makes them very applicable for very fast filtering when implemented in fixed-point arithmetic. However, although the mat...

Multirate systems play an important role in modern telecommunication. Examples of their application are lter banks for image or speech coding, transmultiple-xers, sampling rate converters, and block processing systems. Usually they are designed under idealizing assumptions , neglecting wordlength eeects as well as the required coding between analysis and synthesis part of the multirate system. ...

Sliding window formulations of the fast QR and fast QR-lattice algorithms are presented. The derivations are based on the partial triangularization of raw data matrices. Three methods for window downdating are discussed: the method of plane hyperbolic rotations, the Chambers’ method, and the LINPACK algorithm. A numerically ill-conditioned stationary signal and a speech signal are used in finit...

In a 1961 paper, Box and Hunter defined the resolution of a regular fractional factorial design as a measure of the amount of aliasing in the fraction. They indicated that the maximum resolution is equal to the minimum length of a defining word. Since then, various approaches have been offered to generalize the concept of resolution to arbitrary (possibly mixed-level) fractions. These have gene...

Currently there are design barriers inhibiting the implementation of high-precision digital signal processing (DSP) objects with field programmable logic (FPL) devices. This paper explores overcoming these barriers by fusing together the popular distributed arithmetic (DA) method with the residue number system (RNS) for use in FPL-centric designs. The new design paradigm is studied in the conte...

Traditional filter design (i.e. through the use of the q-operator), gives relatively good results when the sampling frequency is moderate. On the other hand, when the sampling frequency increases, the filter starts performing poorly. This applies not only to finite wordlength effects, but also to the connection between the digital (sampled) system and the underlying continuous-time system. To o...

H. Aboushady, Y. Dumonteix, M. M. Louërat and H. Mehrez Université Paris VI, Laboratoire LIP6/ASIM 4, Place Jussieu, 75252 Paris Cedex 05, France Email: [email protected] , [email protected] Abstract—A power efficient multi-rate multi-stage Comb decimation filter for mono-bit and multi-bit A/D converters is presented. Polyphase decomposition in all stages, with high decimation fa...

Fermat and Mersenne N T T s are relatively easy to implement, but unsuitable for many DSP applications, due to small block length over wordlength. This paper presents VLSI design techniques appropriate for a wider range of N T T s , including maximum-length N T T s , and presents a systolic architecture exploiting blocklength factorisation to decompose the architecture into sub-modules, themsel...