Soft errors resulting from the impact of charged particles are emerging as a major issue in the design of reliable circuits at deep sub-micron dimensions even at ground level. To face this challenge, a designer must dispose of a variety of mitigation schemes adapted to their specific design constraints. Built In Current Sensors have been proposed as a detection scheme for single event upsets in...

An 8bit two-step time-to-digital converter (TDC) with a novel digital switched ringoscillator based time amplifier (TA) is demonstrated in 65nm CMOS. The proposed TA achieves a predictable and programmable gain without requiring any calibration. The implemented 8bit two-step TDC with a 16x TA gain achieves a time resolution of 2.6ps at 80MS/s conversion rate while consuming 2mW. The measured DN...

An SRAM reliability test macro is designed in a 1.2V, 65nm CMOS process for statistical measurements of Vmin degradation. An automated test program efficiently collects statistical Vmin data and reduces test time. The proposed test structure enables Vmin degradation measurements for different SRAM failure modes such as the SNM-limited case and the access-time-limited case. The impact of voltage...

increases with the scaling of CMOS technology, is not explicitly With scaling of technology feature sizes, the share of leakage in toaddressed using this technique. Consequently, the effectiveness of tal power consumption of digital systems continues to grow. Contraditional voltage and frequency scaling is limited with advanceventional dynamic voltage scaling (DVS) techniques fail to accument o...

To satisfy the demand for inter chip interconnects bandwidth, current research projects are based on use of wave guided optical interconnects. The circuit is implemented to compensate high external capacitive loads. A maximum of 12 channels LASER diode each 10 GB/s is designed to reduce power consumption. The layout area, adjustable modulation current and bias current are achieved. Design can b...

This paper presents a new aging sensor architecture for error prediction of performance errors in synchronous digital circuits. The aging sensor is based on a new flip-flop with built-in logic that predicts the errors by monitoring long-term performance degradation of CMOS digital systems. The main advantage is that the sensor’s long-term degradation effects increase its sensitivity to performa...