In analog integrated circuits, process variations result in physical parameter variations. Simulated performance values must then be considered with their tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either ’0’ or ’1’ such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits fault detectability is still a vague...

The paper presents an analogue front-end and ADC integrated circuit for processing signals of sensors implanted into joint prosthesis. The circuit is designed to be operated with Wheatstone bridge sensors, such as strain gauges, pressure, Hall Effect, magneto-resistive sensors, etc. It performs sensor supply multiplexing, sensor signal amplification with chopper modulation, offset compensation ...

The auth6rs have applied a simple modelling approach for multiple resonant tunnelling transistors (mRTTs) which includes four resonant tunnelling diodes (RTDs) within the transistor structure. Unique features of this model, corresponding to device features compatible for integrated circuits, allow for tuning and matching the devices for optimum circuit performance. Two circuits are presented fo...

Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. It is highly desirable to automate the transistor sizing process towards being able to rapidly design high performance integrated circuit. Presented here is a simple but effective algorithm for automatically optimizing the circuit parameters by exploiting the ...

The increasing complexity of circuit design needs to be managed with appropriate optimization algorithms and accurate statistical description of design models in order to reach the design specifics, guaranteeing ’’zero defects’’. In the Design for Yield open problems are the design of effective optimization algorithms and statistical analysis for yield design, which require time consuming techn...

This work presents a technique for the onchip generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. The proposed generation technique consists of a modified low-order analog filter, that provides a sinusoidal output as response to a DC input, combined with a harmonic cancellation strategy to improve the linearity of the generated signal. The propose...

In this chapter, a multi-objective design methodology for automatic analog integrated circuits (IC) synthesis, which enhances the robustness of the solution by varying technological and environmental parameters, is presented. The automatic analog IC sizing tool GENOM-POF was implemented and used to demonstrate the methodology, and to verify the effect of corner cases on the Pareto optimal front...

Supply Current Testing (IDDQ) has become an important defect oriented test strategy for digital IC products. The technique takes advantage of the low quiescent supply current drawn by static CMOS circuits relative to the current consumption during state changes. However, in analogue and mixed signal IC’s this condition can rarely be observed, as in most circuits, steady state currents depend on...

In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and p...