This paper discusses research challenges in developing methodologies and tools for the synthesis and analysis of a key component in portable digital communications and multimedia consumer electronics systems, namely, application-specific processors and associated compilers. For such applications it is typically desirable to implement functionality in software, however the penalty in cost/effici...

GOALS System level design involves a series of tradeoffs in determining the best way to implement a particular task in the hardware/software design space. ASIC implementations can be optimized for a variety of parameters including execution speed, throughput, or power consumption, but do not offer any flexibility as far as future applications are concerned. This inflexibility often leads to low...

ASIP processors and programmable accelerators are replacing monolithic ASICs in more and more areas. However the design and implementation of a new ASIP processor or programmable accelerator requires a substantial design effort. There are a number of existing tools that promise to ease this design effort, but using these tools usually means that the designer get locked into the tools a priori a...

MorphoSys is a reconfigurable architecture for computation intensive applications. It combines both coarse grain and fine grain reconfiguration techniques to optimize hardware, based on the application domain. M2, the current implementation, is developed as an IP core. It is synthesized based on the TSMC 0.13 micron technology. Experimental results show that for multimedia applications MorphoSy...

S. Lüders, R. Baldinger, D. Baumeister, K. Bösiger, R. Eichler, M. Feuerstack–Raible, C. Grab, S. Löchner, B. Meier, P. Robmann, B.A. Schmid, U. Stange, S. Steiner, U. Straumann, S. Streuli, K. Szeker P. Truöl Institute for Particle Physics, ETH Zurich, 5232 Villigen PSI, Switzerland ASIC–Laboratory, Kirchhoff–Institute for Physics, 69120 Heidelberg, Germany Physics Institute, University of Zur...

The scope of this work is to present a solution to implement a remote electronic laboratory for testing and designing analog ASICs (ispPAC10). The application allows users to create circuit schematics, upload the design to the device and perform measurements. The software used for designing circuits is the PAC-Designer and it runs on a Citrix server. The signals are generated and the responses ...

Introduction The use of vectorless test techniques for detecting and isolating process related circuit board faults for IC devices has become widely accepted as the method of first choice because of their cost savings. However, for high fault coverage, most vectorless techniques must be supplemented with expensive functional test methods. A vectorless test technique has been developed that uses...

Area-array bonding technology (i.e. Flip-chip, C4) was pioneered by IBM in the late 1960’s as an alternative to periphery bonding technology (i.e. wire-bond). In recent years, several commercial companies have started offering bumping and flip-chip services. Flip-chip technology is expected to grow at at compound annual growth rate of 38% through the year 2001 [1]. The purpose of this paper is ...

With the growing trend in ASIC design to include more analog functions on chip, various design support and automation efforts have arisen to address the analog design concerns. Existing hardware description languages have been widely used for design representation, documentation and transfer mainly in the digital domain, with standards such as VHDL being fairly mature. In this paper we present ...

This study reports a new stacking method for assembling a 3-D microprobe array. To date, 3-D array structures have usually been assembled with vertical spacers, snap fasteners and a supporting platform. Such methods have achieved 3-D structures but suffer from complex assembly steps, vertical interconnection for 3-D signal transmission, low structure strength and large implantable opening. By a...