Advances in the configurable logic fabric’s architecture, together with the increasing hard-wired integration of commonly used cores such as giga-bit I/O transceivers, multipliers and processors suggests that statically configured FPGA platforms will continue to become more competitive and therefore gain further market share at the expense of the ASIC. In addition, the Semiconductor Association...

Mathematical analysis and empirical evaluation of the solid state equation PowerCMOS = P = C ⋅V2 ⋅ f ⋅ N ⋅%N is presented in this paper which identifies a measurable metric for evaluating relative advantages of ASIC, DSP, and RISC architectures for embedded applications. Relationships are examined which can help predict relative future architecture performance as new generations of CMOS solid s...

Personal monitoring systems require sampling and processing on multiple streams of physiological signals to extract meaningful information. These systems require a large number of digital signal processing and machine learning kernels which typically require significant amounts of power. However, to be used in a wearable environment, the processing system needs to be low-power, real-time, and l...

BACKGROUND Modern EIT systems require simultaneously operating multiple functions for flexibility, interoperability, and clinical applicability. To implement versatile functions, expandable design and implementation tools are needed. On the other hand, it is necessary to develop an ASIC-based EIT system to maximize its performance. Since the ASIC design is expensive and unchangeable, we can use...

A high-performance ASIC has been developed to serve as the interface for the 10-ns bus in the new AlphaServer 8000 series server systems from Digital. The CMOS standard-cell alternative (CSALT) technology provides a timing-driven layout methodology together with a correct-by-construction approach for managing the complex device physics issues associated with state-of-the-art CMOS processes. The...

We present a high performance edge detection architecture for real-time image processing applications. The architecture is nely pipelined. The proposed ASIC is capable of producing one edge{pixel every clock cycle. At a clock rate of 10 MHz, the architecture can process 30 frames per second, where the size of each frame is 640 480 8{bit pixels. The ASIC was laid out and fabricated using Samsung...

Abstract: Logic function realization using Reed-Muller (RM) expression has manifold advantages over realization using SOP expression. In this paper, we present an ASIC architecture for generating optimum 3-variable mixed polarity RM expression. The ASIC based minimization is much faster than the software based minimization. The design is modeled using Verilog HDL and synthesized using Quartus I...

Monolithic Active Matrix with Binary Counters (MAMBO) V ASIC has been designed for detecting and measuring low energy X-rays. A nested well structure with a buried n-well (BNW) and a deeper buried p-well (BPW) is used to electrically isolate the detector from the electronics. BNW acts as an AC ground to electrical signals and behaves as a shield. BPW allows for a homogenous electric field in th...

Future detectors for high luminosity particle identification and ultra high energy neutrino observation would benefit from a digitizer capable of recording sensor elements with high analog bandwidth and large record depth, in a cost-effective, compact and low-power way. A first version of the Buffered Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons learned from the ...

The level of integration has been rapidly increasing with advances in semiconductor technology. Many HP design groups have capitalized on this capability to create highly integrated ASICs, or superchips. Superchips that integrate conventional ASIC logic, microprocessors, embedded RAM and ROM, and other megacell functions save cost, power, board space, and inventory overhead and increase I/O per...