This paper draws on systemic functional linguistic genre analysis to illuminate the way in which post graduate applied linguistics students structure their argumentation within a multi party asynchronous computer mediated conference. Two conference discussions within the same postgraduate course are compared in order to reveal the way in which computer-based argumentation may differ from that o...

This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID (“Revolving Asynchronous Pentium® Processor Instruction Decoder”), a prototype IA32 instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25μ CMOS process and tested...

The purpose of this paper is to propose a design technique for improving the resistance of the Quasi Delay Insensitive (QDI) Asynchronous logic against Differential Power Analysis Attacks. This countermeasure exploits the properties of the QDI circuit acknowledgement signals to introduce temporal variations so as to randomly desynchronize the data processing times. The efficiency of the counter...

In this research communication, we comment on “Dual-rail asynchronous logic multi-level implementation” [Integration, the VLSI Journal 47 (2014) 148-159] by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multi-level decomposition, and physical implementation.

The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification. This information is used throughout the synthesis procedure to optimize the design. In order to synthesize a timed circuit, it is necessary to explore the timed s...

Asynchronous circuits based on Current-Sensing Completion Detection (CSCD) are an efficient alternative to known dual rail coding techniques in terms of area required, operating speed and power consumption. New BiCMOS Current-Sensing Circuits (CSC’s) which fully support the advantages of CSCD are presented. Multiple localised CSC’s are studied and an example of a 4-bit parallel multiplier is in...

Given a timed automaton with parametric timings, our objective is to describe a procedure for deriving constraints on the parametric timings in order to ensure that, for each value of parameters satisfying these constraints, the behaviors of the timed automata are time-abstract equivalent. We will exploit a reference valuation of the parameters that is supposed to capture a characteristic prope...

This paper draws on systemic functional linguistic genre analysis to illuminate the way in which post graduate applied linguistics students structure their argumentation within a multi party asynchronous computer mediated conference. Two conference discussions within the same postgraduate course are compared in order to reveal the way in which computer-based argumentation may differ from that o...

In a synchronized network of n nodes, each node will update its parameter based on the system state in a given iteration. It is well-known that the updates can converge to a fixed point if the maximum absolute eigenvalue (spectral radius) of the n × n iterative matrix F is less than one (i.e. ρ(F) < 1). However, if only a subset of the nodes update their parameter in an iteration (due to delays...