Asynchronous Fine-grain power gated Logic (AFL) which includes Modified Efficient Charge Recovery Logic (M-ECRL) gates to implement the logic function of the stage with a handshake controller which comprises of C-element to handle the control signals with the neighboring stages and provides power to MECRL gate. AFL adopts an partial charge reuse (PCR) mechanism, part of the charge on the output...

A novel design method of asynchronous domino logic pipeline, which focuses on improving the circuit efficiency and making asynchronous domino logic pipeline design more practical for a wide range of applications. The data paths are composed of a mixture of dual-rail and single-rail domino gates. Dual-rail domino gates are limited to construct a stable critical data path. Based on this critical ...

Solvability of the model matching problem for input/output switched asynchronous sequential machines is discussed in this paper. The control objective is to determine the existence condition and design algorithm for a corrective controller that can match the stable-state behavior of the closed-loop system to that of a reference model. Switching operations and correction procedures are incorpora...

Based on the impς-calculus, ASP (Asynchronous Sequential Processes) defines distributed applications behaving deterministically. This article extends ASP by building hierarchical and asynchronous distributed components. Components are hierarchical a composite can be built from other components, and distributed a composite can span over several machines. This article also shows how the asynchron...

Asynchronous logic is a hot topic due to its interesting features of power saving, low noise and robustness to parameters variations. However, its performance analysis is relatively complex. In fact, the handshaking protocol strongly influences the performance of the pipelined architectures. This paper introduces verified Standard-Logic schematics for QDI asynchronous latches and analyzes their...

Many styles of asynchronous circuits are mathematically fascinating, but practically useless. In particular, “delay insensitive” circuits which make no assumptions whatsoever about the relative delays of elements are generally useless because they involve tremendous overhead determining when logic has completed. We will avoid these types of circuits and focus on circuits which make a limited nu...

We present a novel asynchronous RSFQ digital circuit, Test-Timed RSFQ digital circuit and system(TT), in this paper. With this asynchronous approach, data is transferred in a delay-insensitive fashion to avoid the overhead of global clock distribution and the timing uncertainty. According to the scheme, the timing signal of the logic module is generated by a test logic module. The delay module ...

This paper presents an efficient asynchronous design methodology for synchronous FPGAs. The mixed synchronous/asynchronous design is the best way to minimize the power consumption of a circuit implemented on a synchronous FPGA. For asynchronous circuit synthesis, Balsa was proposed. However, the problem is that circuits synthesized from Balsa description need a lot of logic resources. To solve ...

Two fairly intuitive conditions are given that serve to algebraically characterize Seitz's "weak conditions" for self timed circuits. It is shown that these two conditions embody the 12 temporal logic conditions (developed by Owicki and Malachi) which are intended to express both the weak conditions as well as certain liveness properties that self timed circuits need to satisfy. This research w...