We present a new test generation procedure for sequen tial circuits using spectral techniques Iterations of lter ing via compaction and spectral analysis of the ltered test set are performed for each primary input extracting in herent spectral information embedded within the test se quence This information when viewed in the frequency domain reveals the characteristics of the input spectrum The...

The ever-increasing complexity and size of current circuit designs have made testing and verification major bottlenecks in the design flow of VLSI (Very Large Scale Integrated) circuits. Statistics show that more than 70% of the design effort can be spent on functional verification and manufacturing testing. This percentage is expected to increase in the future if no significant strides in thes...

An ATPG algorithm based on a special class of BDD models, called Structurally Synthesized BDDs (SSBDD), is presented. Experimental results show that the novel test generation approach provides a remarkable speed-up in comparison with classical gate-oriented methods. In addition, SSBDDs offer a more generalized view to the test generation problem.

In this paper, we propose a technique that utilizes the genetic algorithm for various VLSI circuits. In GA, we proposed the method of automatic test pattern generation (ATPG) is used to generate test vectors. Experiment results showed that the proposed algorithm reduce the complexity of the circuits and also the execution time. The design is realized using VHDL and then fabricated on FPGA.

T est generation for today’s complex digital cir cuits is an extr emely computation intensive task. The search space of ATPG can be reduced by starting from higher level circuit descriptions. The integration of alternate testing methodology IDDQ testing is suggested for increasing the efficiency of a high level VHDL based test generator.

Sensor network, unlike traditional communication network, is deeply embedded in physical environments and its operation is mainly driven by the event activities in the environment. In long-term operations, the event activities usually show certain patterns which can be learned and exploited to optimize network design. However, this has been underexplored in the literature. One work related to t...

Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size and complexity. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Since ATPG is an NP complete problem with complexity exponential to circuit size, the application of parallel processing techniques to ...

This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often fail when highly sequential subnetworks are found. On the other hand, symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or medium circuits, no matter their s...

This paper describes a functional test pattern generator which exploits two different paradigms: high-level decision diagrams (HLDDs) and extended finite state machines (EFSMs). HLDDs and EFSMs are deterministically explored by using propagation, justification, learning and backjumping. The integration of such strategies allows the ATPG to more efficiently analyze the state space of the design ...