We demonstrate a tunable electron-blocking layer to enhance the performance of an Earth-abundant metal-oxide solar-cell material. A 5 nm thick amorphous ternary metal-oxide buffer layer reduces interface recombination, resulting in sizable open-circuit voltage and efficiency enhancements. This work emphasizes the importance of interface engineering in improving the performance of Earth-abundant...

This paper addresses the issues of power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimising short circuit power and subthreshold leakage power which is predominant when

An improved analytical model for IGB power transistors has been developed for circuit simulators. Special attention is paid to the physical modeling of the short channel in the DMOS branch and the buffer layer near the anode in IGBT device structures. Good agreement between simulated and measured data has been obtained.

In this paper, an industrial application of symbolic modeling methods to the design of interface circuits is presented. A modeling method based on circuit knowledge and performance-oriented error estimation is used for an automatic generation of analog behavioral models. Results calculated with an output buffer show the effectiveness of this approach.

We demonstrate a compact optical buffer module, comprising an InP 1×8 phased-array switch and a silica-based delay line circuit. Tunable and uniform buffering of up to 21 ns is obtained with a 3-ns temporal resolution. ©2012 Optical Society of America OCIS codes: (130.3120) Integrated optics devices; (130.4815) Optical switching devices; (060.1810) Buffers, couplers, routers, switches, and mult...

This paper provides a voltage mode (VM) multi input single output (MISO) universal filter with the help of voltage differencing inverting buffer amplifier (VDIBA). All the filter functions i.e., Low pass, band pass, band reject, high pass, and all pass filter functions can be realized without modifying the circuit configuration. The pole frequency can be independently tunable by its transconduc...

Any integrated system consists of a host processor, memory and peripheral elements which are interconnected through a bus interface. The synchronization of these basic blocks with internal and external environment is achieved by means of an I/O buffer. The work is intended to develop a self-reconfigurable channel data buffering form and circuit design for network-on-chips (NoCs). The design is ...

Abstract: In this paper the design of a high voltage tolerant and reliable CMOS I/O buffer is proposed without using thick-oxide devices. In this presented design for mixed low voltage interface applications, it uses a simpler structure and therefore the circuit has good gate-oxide reliability. In addition, it is free of dc leakage current. No additional pad for dual power supplies is required ...

A 2.4-GHz CMOS on-off keying (OOK) transmitter is developed for applications that require high data rate over 10Mbps in the area of wireless body area network (WBAN) and medical implant communication service (MICS). A novel analog pulse-shaping circuit for reducing power consumption and circuit complexity is employed for the OOK transmitter. Fabricated in 0.13μm CMOS, the transmitter core exclu...

An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal v...