Technology CAD has already proven to be an attractive and indispensable supplement to standard process development methodologies for VLSI technology. The flexibility and versatility of TCAD makes it ideally applicable for smart power technology to cut down development costs and cycle times. The Vienna Integrated System for TCAD Applications is a simulation environment which offers great flexibi...

The Freeware Alliance CAD system is a set of technology independent libraries plus a set of tools dedicated to digital CMOS vlsi design. We present an overview of the functionalities available within the system libraries, including VHDL behavior, netlist and symbolic layout views for all cells. Both standard cells libraries and custom block generators are detailed, since it is a unique feature ...

Binary Decision Diagrams (BDDs) are useful data structures for symbolic Boolean manipulations. BDDs are used in many tasks in VLSI/CAD, such as equivalence checking, property checking, logic synthesis, and false paths. In this paper we describe a new approach for the realization of a BDD package. To perform manipulations of Boolean functions, the proposed approach does not depend on the recursi...

The problem of synthesis of Petri nets from transition systems or languages has many applications, ranging from CAD for VLSI to medical applications, among others. The most common algorithms to accomplish this task are based on the theory of regions. However, one of the problems of such algorithms is its space requirements: for real-life or industrial instances, some of the region-based algorit...

In this work, we propose a method for using simulation to analyze the robustness of multiparty (multicastbased) protocols in a systematic fashion. We call our method Systematic Testing of Robustness by Examination of Selected Scenarios (STRESS). STRESS aims to cut the time and effort needed to explore pathological cases of a protocol during its design. This paper has two goals: (1) to describe ...

The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other...

The Pittsburgh Digital Greenhouse is sponsoring an educational support program to facilitate student IC design projects and laboratories at Carnegie Mellon University, the Pennsylvania State University, and the University of Pittsburgh. Students who have access to industry standard IC design tools that are integrated in a commercial design flow will be better prepared to enter the workforce. Ho...

In this paper we present a family of multi-objective hypergraph partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both the cut and the maximum subdomain degree are simultaneously minimized. This type of partitionings are critical for existing and emerging applications in VLSI CAD as they allow to both minimize and evenly distribute the i...

Although routing is a well-studied problem in various contexts, there remain unsolved problems in routing edges for graph layouts. In contrast with techniques from other domains such as VLSI CAD and robotics, where physical constraints play a major role, aesthetics play the more important role in graph layout. For graphs, we seek paths that are easy to follow and add meaning to the layout. We d...

Logic partitioning is an important area of VLSI CAD, and there have been numerous approaches proposed. Logic replication, the duplication of logic in order to minimize communication between partitions, can be an effective component of a complete partitioning solution. In this paper we seek a better understanding of the important issues in logic replication. By adding new optimizations to existi...