Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI digital signal processing (DSP) systems. One of the most widely used operations in DSP is finite-impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a progra...

In this paper, a high speed and low power 16x16 Vedic Multiplier is designed by using low power and high speed modified carry select adder. Modified Carry Select Adder employs a newly incremented circuit in the intermediate stages of the Carry Select Adder (CSA) which is known to be the fastest adder among the conventional adder structures. A Novel technique for digit multiplication namely Vedi...

Received Oct 16, 2017 Revised Dec 12, 2017 Accepted Jan 4, 2018 Filter is one of the key components of all signals processing elements. Both the FIR and IIR filter are used to reduce the unwanted signal in the original signal. Here discussing the FIR filter and design the efficient FIR filter using Dual Ripple Carry Adder (RCA) based SQRT-carry select adder (CSLA). Many components present in th...

In performing fast arithmetic functions, Carry select adder (CSLA) is one of used in many data processing processors to perform fast arithmetic functions. Adders are the basic building blocks in digital integrated circuit based designs. Ripple carry adders are slowest adders as every full adder must wait till the carry is generated from previous full adder. CSLA (SQRT CSLA) architecture have be...

Booth encoded Multiplier is used to reduce the hardware utilization in chip level designing in VLSI projects. The present project is focusing on designing and developing a powerful Booth encoded multiplier integrated with Carry Select Adder [CSLA]. Primarily the on hand Booth encoding multiplier is used in multiplication operations based on signed numbers only. The multipliers such as braun arr...

The comparator is a very basic and useful arithmetic component of digital systems. An individual, compact, high-performance, good cost-benefit ratio comparator core plays an important role on almost all hardware sorters. The study proposes a tine cost-performance ratio comparator design. Based on modified 1’s complement principle and conditional sum adder scheme, the proposed design has small t...

This paper analyses techniques to measure the delay of 64 bit and 128-bit carry select adders .This is used for high-performance and low-power applications. It is introduced to work at a lower time delay than that required by a Ripple Carry Adder. This paper uses a very simple and efficient gate-level modification technique to significantly reduce the delay of the CSA. The proposed design has r...

In this paper, we have proposed a modified carry select adder which is known as fastest adders that can perform arithmetic operations in Digital signal processors. Modification in the gate level of the Square root Carry Select Adder (SQRT CSLA) structure results in the reduction of area and power of the CSLA structure which offers a simple and efficient function. Depending upon the Regular SQRT...

A redundant binary (RB) representation is used for designing high performance multiplier. Because of its high modularity and carry free addition. The error correcting word (ECW) plays an important role in redundant binary multiplier. The redundant binary (RB) coding and modified booth (MB) encoding creates the error correcting word. The extra error correcting is eliminated by combining the erro...