نتایج جستجو برای: cavity layout design

تعداد نتایج: 1048306  

2005
Jan Osburg Dimitri Mavris

The Aerospace Systems Design Laboratory at the Guggenheim School of Aerospace Engineering, Georgia Institute of Technology, has recently created the "Collaborative Design Environment" (CoDE), a nextgeneration design facility supporting efficient, rapidturnaround conceptual design. The CoDE combines cost-effective, off-the-shelf information technology with advanced design methodologies and tools...

A. Jayant Kulkarni, S. Kazemzadeh Azad ,

The present study is an attempt to propose a mutation-based real-coded genetic algorithm (MBRCGA) for sizing and layout optimization of planar and spatial truss structures. The Gaussian mutation operator is used to create the reproduction operators. An adaptive tournament selection mechanism in combination with adaptive Gaussian mutation operators are proposed to achieve an effective search in ...

Journal: :Structural and Multidisciplinary Optimization 2019

Journal: :INTERNATIONAL JOURNAL OF INDUSTRIAL ENGINEERING RESEARCH AND DEVELOPMENT 2016

Journal: :IEEJ Transactions on Electronics, Information and Systems 1988

Journal: :IEEE Transactions on Visualization and Computer Graphics 2021

Modeling layout is an important first step for graphic design. Recently, methods generating layouts have progressed, particularly with Generative Adversarial Networks (GANs). However, the problem of specifying locations and sizes design elements usually involves constraints respect to element attributes, such as area, aspect ratio reading-order. Automating attribute conditional remains a comple...

A new approach for designing an ultra wideband (UWB) CMOS low noise amplifier (LNA) is presented. The aim of this design is to achieve a low noise figure, reasonable power gain and low power consumption in 3.1-10.6 GHz. Also, the figure of merit (FOM) is significantly improved at 180nm technology compared to the other state-of-the-art designs. Improved π-network and T-network are used to obt...

1995
Venkat K. R. Chiluvuri

Several yield enhancement techniques are proposed for the last two stages of VLSI design, i.e., topological/symbolic and physical layout synthesis. Our approach is based on modiications of the symbolic/physical layout to reduce the sensitivity of the design to random point defects without increasing the area, rather than fault tolerance techniques. A layout compaction algorithm is presented and...

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