نتایج جستجو برای: circuit optimisation

تعداد نتایج: 134398  

2007
B. Cannas A. Fanni M. Marchesi F. Pilo

A general purpose implementation of the Tabu Search metaheuristic, called Universal Tabu Search, is used to optimally design a Locally Recurrent Neural Network architecture. In fact, generally, the design of a neural network is a tedious and time consuming trial and error operation that leads to structures whose optimality is not guaranteed. In this paper, the problem of choosing the number of ...

Journal: :IET collaborative intelligent manufacturing 2022

Research on Reconfigurable Battery Systems (RBS) is gaining emphasis over the traditional fixed topology of battery pack due to its advantages adapting flexible (series-parallel) during operation in for meeting non-linear time-dependent load requirements. There could emerge serious issues such as those related safety malfunction switching circuit, heat generation from switches frequent circuits...

2007
L. LABRAK

This paper presents a new method to improve analog design automation and thus design reuse. A topdown constraint driven methodology is applied to design complex analog system. This approach formulates the design problem as a multi objective optimization problem (MOOP). In the last decades optimization has been introduced in the field of analog design. Nevertheless, the knowledge needed to build...

2016
M. J. BURKE

This paper reports the optimisation of the low-frequency response of a multi-stage bioelectric amplifier intended for use in the measurement of the electrocardiogram (ECG) using un-gelled electrodes. The frequency response was optimised to meet the International Electrotechnical Commission 60601 performance standards for electrocardiographs [1,2]. The low frequency response of a multi-stage amp...

2001
R. Micheloni

The typical characteristic of flash memory technology, its flexibility, is seen as the main factor that explains the strong evolution of its demand, continuously generating new applications with the typical pervasiveness of the innovative semiconductor products. But the flexibility also determines the peculiar position of this product in the market. Flash memories are not a dedicated product, b...

2010
Sergio Callegari Federico Bizzarri

An example of how circuit related techniques can help solving optimisatin problems originating from completely different domains is provided. It is shown that a specific class of Unconstrained Binary Quadratic Programming (UBQP) problems, including those arising in the optimisation of flutter control via blade mistuning, can be solved by means of ∆Σ modulators. This is done in steps, first rest...

2015
Jaswinder Lota Andreas Demosthenous

The paper details on-chip inductor optimization for a reconfigurable continuous-time delta-sigma (Δ-Σ) modulator based radio-frequency analog-to-digital converter. Inductor optimisation enables the Δ-Σ modulator with Q enhanced LC tank circuits employing a single high Q-factor on-chip inductor and lesser quantizer levels thereby reducing the circuit complexity for excess loop delay, power dissi...

2002
Dinesh Pamunuwa Hannu Tenhunen

Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnect. In deep sub-micron technologies, as the wires are spaced ever closer and signal rise and fall times go into the sub-nano second region, increased cross talk has implications on the data throughput and on signal integrity. Depending on the data correlation on the coupled lines, ...

1998
Francisco Azevedo Pedro Barahona

In a faulty digital circuit, many (single) faulty gates may explain the observed findings. In this paper we are mostly concerned, not in obtaining alternative diagnoses, but rather to differentiate the available candidates. Although techniques exist that generate test patterns for verifying whether one specific gate is faulty, these techniques do not identify test patterns that discriminate bet...

2004
P.

The paper investigates the layout optimisation problem for processor-array networks. If an appropriate shape geometry is selected for the processors, a specific interconnection network can be area-eficiently mapped on a VLSI/WSI chip to maximise the chip yield, operational reliability and circuit performance. A formal technique of cellular layout by polyomino tiles is proposed, with application...

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