The design of a synchronous system having a global clock must account for the phase shifts experienced by the clock signal (clock skew) in its distribution network. As clock speeds and system diameters increase, this requirement becomes increasingly constraining on system designs. Two currently used approaches to this problem are to minimize skew by equalizing electrical path delays, and to re-...

A novel approach for minimizing power during scan testing is presented. The idea is that given a full scan module or core that has multiple scan chains, the test set is generated and ordered in such a way that some of the scan chains can have their clock disabled for portions of the test set. Disabling the clock prevents flip-flops from transitioning, and hence reduces switching activity in the...

In present time weighted suffix tree is consider as a one of the most important existing data structure used for analyzing molecular weighted sequence. Although a static partitioning based parallel algorithm existed for the construction of weighted suffix tree, but for very long weighted DNA sequences it takes significant amount of time. However, in our implementation of dynamic partition based...

Title of dissertation: PHYSICAL DESIGN METHODOLOGIES FOR LOW POWER AND RELIABLE 3D ICs Tiantao Lu, Doctor of Philosophy, 2016 Dissertation directed by: Professor Ankur Srivastava Department of Electrical Engineering As the semiconductor industry struggles to maintain its momentum down the path following the Moore’s Law, three dimensional integrated circuit (3D IC) technology has emerged as a pr...

We consider the problem of automatically verifying realtime systems with continuously distributed random delays. We generalise probabilistic timed automata introduced in [19], an extension of the timed automata model of [4], with clock resets made according to continuous probability distributions. Thus, our model exhibits nondeterministic and probabilistic choice, the latter being made accordin...

A robust physical design of 3D-IC requires investigation on through-silicon-via (TSV). The large temperature and stress gradients can severely affect TSV delay with large variation. The traditional physical model treats TSV as resistor with linear electrical-thermal dependence, which ignores the fundamental device physics. In this paper, a physics-based electrical-thermal-mechanical delay model...

Wave pipelining is an attractive technique used in high-speed digital circuits to speed-up pipeline clock-rate by eliminating the synchronizing elements between pipeline stages. Wave-pipelining has been successfully applied to the design of CMOS multipliers [1, 2, 11, 10, 12] which have demonstrated speed-ups of clock-rate 4 to 7 times over their nonpipelined design. In order to achieve high cl...

A 64 X64-bit iterating multiplier, the Stanford Pipelined Iterative Multiplier (SPIM), is presented. Tbe pipelined array consists of a small tree of 4:2 adders. The 4:2 tree is better suited than a Wallace tree for a VLSI implementation because it is a more regular structure. A 4:2 carry-save accumulator at the bottom of the array is used to iteratively accumulate partial products, allowing a p...