Highlighting the dominance & supremacy of CMOS digital logic design over its counterparts & further coming up with a unique solution to minimize the power losses prevalent in switching implementations using CMOS, this brief introduces a novel SDLC (Switching-DiodeInductor-Capacitor) design. It presentsa design which in ideal case may lead to a circuit capable of performing logic operations with...

A novel high-speed circuit implementation of the (31,5)-parallel counter (i.e., population counter) based on capacitive threshold logic (CTL) is presented. The circuit consists of 20 threshold logic gates arranged in two stages, i.e., the parallel counter described here has an effective logic depth of two. The charge-based CTL gates are essentially dynamic circuits which require a periodic refr...

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing shortcircuit current by a piece-wise linear function and considering a current owing from input node to output node through gate capacitances, the accuracy is improved signi cantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experime...

A high reliability complementary metal–oxide–semiconductor (CMOS) winner-takes-all/ loser-takes-all circuit of O(N) complexity with programmable capability is designed. Based on the proposed architecture, the precision of the circuit is independent of the number of inputs. This circuit is easily programmed for WTA or LTA function by an enable signal, without modifying the circuit structure or p...

Many single-electron devices and circuits that realize CMOS-like digital logic were proposed so far (Takahashi, Ono, Fujiwara, & Inokawa, 2002). However, the single-electron circuit technology should aim at developing computing systems that perform information processing by using singleelectron phenomena (Morie, & Amemiya, 2006). Because their operation principles are completely different from ...

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to Vdd. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output ...

Superconductive single-flux-quantum (SFQ) circuit technology attracts attention as a next generation technology of integrated circuits because of its ultra-fast computation speed and low power consumption. In SFQ digital circuits, unlike CMOS digital circuits, a pulse is used as a carrier of information and the representation of the logic values is different from that in CMOS digital circuits. ...

Abstract Decreasing power consumption is the leading challenge for very-large-scale-integrated (VLSI) designers. This paper introduces an innovative prototype a power-efficient standard or fully-adiabatic binary-coded-decimal (BCD) 8421 to Excess-3 (XS-3) code converter. The proposed design compared with traditional complementary metal oxide semiconductor (CMOS) as well two popular fully adiaba...

The new technologies are giving the advance systems which are capable to perform multiple operations simultaneously. This all is possible by the scaling technology where the overall chip size get reduced but due to manufacturing and fabrication defects, certain design uncertainty arises thereby affecting the transistor performance by timing related effect. The robust circuit where sufficient ma...

In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18μm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circui...