Though it is common practice to treat synchronization primitives for multiprocessors as abstract data types, they are in reality machine instructions on registers. A crucial theoretical question with practical implications is the relationship between the size of the register and its computational power. We wish to study this question and choose as a rst target the popular compare&swap operation...

Today’s superscalar microarchitectures use large, heavily-ported physical register files to increase the instruction throughput. The high complexity and power dissipation of such register files mainly stems from the need to maintain each and every result for a large number of cycles after the result generation. We observed that a significant fraction of the result values are delivered to their ...

The profound alterations produced by cocaine on dopamine (DA) neurotransmission raise the possibility that dopamine transporter (DAT)-expressing neurons may modify DA transport in response to repeated cocaine exposure to maintain the appropriate efficiency of DA clearance. In this study, we determined the changes in molecular mechanisms of DAT regulation in rats with a history of repeated cocai...

Introduction: Multiported register files and bypass networks lie at the heart of a superscalar microprocessor core, providing buffered communication of register values between producer and consumer instructions. As issue widths increase, both the number of ports and the number of registers required increase, causing the area of a conventional multiported register file to grow more than quadrati...

Process capability indices CPU and CPL have been widely used in the microelectronics manufacturing industry as capability measures for processes with one-sided specification limits. In this paper, the theory of statistical hypothesis testing is implemented for normal processes, using the uniformly minimum variance unbiased estimators of CPU and CPL. Efficient SAS computer programs are provided ...

To ensure the security of cryptographic algorithm implementations, several key protection schemes have been proposed to prevent various memory disclosure attacks. Among them, register-based solutions do not rely on special hardware features and offer better applicability. However, due size limitation register resources, performance is much worse than conventional cryptosystem implementations wi...

This paper proposes a new register-file architecture that virtualizes logical register contexts. This architecture makes the number of active register contexts—representing different threads or activation records—independent of the number of physical registers. The physical register file is treated as a cache of a potentially much larger memory-mapped logical register space. The implementation ...

This report describes what we believe to be the first attempt to apply integer programming to code scheduling for a clustered architecture. We give an integer linear program (ILP) for instruction scheduling on the Texas Instruments TMS C6X CPU family, which has constraints on the communication between its two clusters. Using CPLEX to solve the ILP, we show that our approach finds shorter schedu...