The concept of fuzzy flip-flop was introduced in the middle of 1980’s by Hirota (with his students). The Hirota Lab recognized the essential importance of the concept of a fuzzy extension of a sequential circuit and the notion of fuzzy memory. From this point of view they proposed alternatives for “fuzzifying” digital flip-flops. The starting elementary digital units were the binary J-K flipflo...

We study the non-negativity conjecture of the complete cd-index of a Bruhat interval as defined by Billera and Brenti. For each cd-monomial M we construct a set of paths, such that if a “flip condition” is satisfied, then the number of these paths is the coefficient of the monomial M in the complete cd-index. When the monomial contains at most one d, then the condition follows from Dyer’s proof...

A clock with adjustable rise and fall time is used in conjunction with a D flip-flop that operates well with this clock. Its intended use is to relax the design of the clock network in digital circuits and to alleviate the problems with simultaneous switching noise in mixed-signal circuits. A test chip has been designed in a 0.35 μm CMOS process. The chip consists of a clock driver with adjusta...

In this paper, based on the coupled-mode and carrier rate equations, a dynamic model and numerical analysis of a multi quantum well (MQW) chirped distributed feedback semiconductor optical amplifier (DFB-SOA)  all-optical flip-flop is precisely derived. We have analyzed the effects of strains of QW and MQW and cross phase modulation (XPM) on the dynamic response, and rise and fall times of the ...

MOS Current-Mode Logic (MCML) is usually used for high-speed applications. In this paper, the design method of the high-speed low-power MCML is addressed. The layout implementations of MCML D-Flip flop cells are presented at a NCSU FreePDK 45nm technology. A mod-10 counter based on the proposed D-Flip flop cells is implemented to verify the efficiency of the proposed design method. The post-lay...

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduces power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors en...

With the technology process scaling, leakage power dissipation is becoming a growing number of percentage in total power dissipation. This study presents a new method in the gate-length biasing technique to achieve a cost-effective gate-length with a most benefit between leakage reduction and delay increasing. With the optimized gate-length, typical combinational and sequential circuits are rea...

The computational properties of second-order lossless discrete integrator/differentiator (LDI/LDD) allpass filters are studied, where the resource requirements in bit-serial hardware implementations are given particular interest. The properties of the LDI/LDD filters are compared to the corresponding properties of second-order wave digital (WD) filters using three-port series adaptors. Two impl...