Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. In particular, lower bounds on a) circuit speed and supply voltage ; b) transition activity in presence of noise; c) dynamic energy dissipation; and d) total (dynamic and static) ...

Multiple-threshold CMOS circuit, which has both high and low threshold transistors in a single chip, can be used to deal with the leakage problem in low voltage low power (LVLP) and high performance applications. The high threshold transistors can suppress the subthreshold leakage current, while the low threshold transistors are used to achieve the high performance. In this paper, we will intro...

Traditionally, area-minimization and speed-maximization were the only factors relative to a design's effectiveness that were measured. Low power, high-throughput, and computationally intensive circuits are also critical application domains\ In addition to these three design parameters; area, speed, and power, there are two design metrics, which have been of great importance to current designs. ...

In this paper we present a comprehensive mathematical analysis of the energy dissipated in deep sub-micron (DSM) buses. The estimation is based on an elaborate bus model that includes all the distributed and lumped parasitic elements that appear as technology scales. The energy drawn from the power supply during the transition of the bus is evaluated in a compact closed form. The notion of acti...

In this paper, we introduce a new encoding scheme that explicitly targets the minimization of the bus energy due to the crosstalk capacitances between adjacent bus lines. The key transformation operated by the code consists of a permutation of the bus lines, implemented directly during physical design; as a desirable consequence, no additional encoding/decoding logic is required at the bus boun...

Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to transistor leakage of low-order and high-order basic logic gates. The NAND and NOR gates have been designed using different design styles and circuit topologies, including complementary CMOS, partitioned logic and complem...

A complete investigation of holographic photonic crystal structures has been conducted. From both theoretical and experimental results, profiles of resultant patterns under different process conditions can be estimated and controlled. The use of antireflection layers is crucial for realizing submicron photonic crystals with good uniformity over a large area. We successfully realize submicron-sc...

A physically based model has been formulated to represent temperature-dependent specific contact resistance. The new model can generate silicided contact resistance values at high temperatures and is capable of predicting high current behavior of silicided deep submicron devices. Implications for failure analysis of advanced silicided devices are also considered. Using the model, it has been de...

A new class of non-totally symmetric functions which can be represented as simple regular symmetric arrays without redundancy is identified. Regular circuits are becoming crucialy important for deep submicron technologies, which needs new layout approaches to fully utilized their potential. The new class of functions contains the classes of totally symmetric and totally symmetric with mixed pol...