Designing wireless sensor networks should meet appropriate parameters such as quality of service (QoS) defined by different users. The variable physical conditions of the environment, processing and transmission power limitations and limited communication capabilities are the most important obstacles that influence QoS parameters such as throughput, delay, reliability and network lifetime. The ...

Voltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product (PDP). Therefore, their lies an optimized ...

We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication and delay reduction, and then introduce the notion of duplication gain for selecting the good candidate gates to be duplicated. The objective is to obtain the maximum delay reduction with the minimum duplications. The...

This paper addresses the issues of power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimizing short circuit power and subthreshold leakage power which is predominant when supply voltage (VDD) and threshold volt...

This paper studies the delay reduction problem for instantly decodable network coding (IDNC)-based device-todevice (D2D) communication-enabled networks. Unlike conventional point-to-multipoint (PMP) systems in which the wireless base station has the sufficient computation abilities, D2D networks rely on battery-powered operations of the devices. Therefore, a particular emphasis on the computati...

A new interleaved synchronous mirror delay (SMD) is proposed in order to reduce the circuit size. The conventional interleaved SMD has multiple pairs of forward delay array (FDA) and backward delay array (BDA) in order to reduce the clock skew. The proposed interleaved SMD requires one FDA and one BDA by changing the position of MUX. Simulation results show that about 30% power reduction and 40...

Delay reduction has become an issue of primary importance in the VLSI industry. Various strategies of delay improvement have been suggested. Buuer Insertion is one such widely used technique. The result obtained by buuer insertion relies heavily on the buuer tree topology on which buuer insertion is done. Avenues for modiica-tion of an existing buuer tree have not been explored. In this paper w...

In this note, we provided an improved way of constructing a LyapunovKrasovskii functional for a linear time delay system. This technique is based on the reformulation of the original system and a discretization scheme of the delay. A hierarchy of Linear Matrix Inequality based results with increasing number of variables is given and is proved to have convergence properties in terms of conservat...