This paper presents pre-layout simulations of a proposed 8T full adder design using a proposed 3T XNOR gate cell. The proposed design remarkably reduces power consumption hence power-delay product (PDP) over various input voltages and frequencies. It also improves temperature sustainability as compared to the existing 8T full adder. This proves to be a viable option for low power and energy eff...

RC4 Stream cipher is well known for its simplicity and ease to develope in software. But here, in the proposed design we have heighlighted the modified hardware implémentation of RC4. As RC4 is the most popular stream cipher. The proposed design performs reading and swapping simultaneously in one clock cycle. The proposed design also highlights the adder part which enhances the architecture spe...

BCD Adder is the fundamental adder we learn in logic design and any basic electronics lab. Conventional BCD Adder what we generally know is not feasible for higher bits as they require more area and as they have more propagation delay for higher bit extension. For higher level application BCD design we require more efficient basic BCD block. So in this paper we proposed 2 types of BCD adders na...

In this paper an extensive study on several adders has been manifested to design VLSI applications. Adder circuits plays a major role to modify or design a multiplier. Imprecise adder is one of the design where used in increasing the performance and power efficiency and approximate adders are for error detection and correction.16T full adders is also used to fast and energy efficient adder. An ...

This paper describes the comparison of VLSI architectures on the basis of Speed, Area and Power of different type of Adders like Carry Chain Adder, Carry Look Ahead Adder, Carry Skip Adder, and Carry Select Adder and 32-bit pipelined Booth Wallace MAC Unit with Carry Chain Adder, Carry Look Ahead Adder, Carry Skip Adder, and Carry Select Adder is designed in which the multiplication is done usi...

This paper presents a design strategy of eliminating signal degradation for memristor ratioed logic (MRL) gates. Based on the strategy, a novel MRL-based one-bit full adder is proposed. The inverters in circuit can effectively eliminate the degradation and restore signal integrity. To evaluate the effectiveness of the proposed one-bit full adder, an eight-bit full adder is demonstrated as a stu...

In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance. A parallel prefix adder involves the execution of the operation in parallel which can be obtained by segmentation into smaller pieces. The binary addition is the basic arithmetic operation in digital circuits and it became essential in most of the digital systems including Arithmetic ...

Adders are some of the most critical data path circuits requiring considerable design effort in order to squeeze out as much performance gain as possible. Various adder structures can be used to execute addition such as serial and parallel structures and most of researches have done research on the design of high-speed, low-area, or lowpower adders. Adders like ripple carry adder, carry select ...

In the recent year, many other new circuits are proposed using less number of transistors with less delay and extremely low power requirement. An adder consisting with less transistors don't give full swing outputs for all input combinations and there is difference in output level for various combinations and these circuits have very low driving capabilities. other circuits also are proposed in...