The 25 nm physical gate length transistor for microprocessor units is scheduled for production on the International Technology Roadmap for Semiconductors (ITRS) roadmap for 2007 [1]. Presently, this pushes device engineers to consider developing such transistors because there is a lag of several years between device design and process integration. This paper reports on the methods and design of...

High performance deep-submicron inversion-mode InGaAs MOSFET with ALD Al2O3 as gate dielectric has been demonstrated. Transistors with gate lengths down to 150 nm have been fabricated and characterized. Record high extrinsic transconductance of 1.1 mS/μm has been achieved at Vds = 2.0 V with 5 nm Al2O3 as gate dielectric. Gm can be further improved to 1.3 mS/μm by reducing the gate oxide thickn...

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output c...

In this paper, novel hybrid MOSFET(HMOS) structure has been proposed to reduce the gate leakage current drastically. This novel hybrid MOSFET (HMOS) uses source/drain-to-gate non-overlap region in combination with high-K layer/interfacial oxide as gate stack. The extended S/D in the non-overlap region is induced by fringing gate electric field through the high-k dielectric spacer. The gate leak...

In this paper, the performance of GaAs and GaSb based sub-10 nm double-gate junctionless metal-oxide-semiconductor field-effect transistors (DG-JLMOSFETs) have been studied for high-performance switching applications. The quantum transmitting boundary method (QTBM) has considered electron transport, band structures are accounted sp3d5s* tight-binding modeling. channel thickness, t <sub xmlns:mm...

Nanosheets are the revolutionary change to overcome limitations of FinFET. In this paper, temperature dependence 10 nm junctionless (JL) nanosheet FET performance on DC and analog/RF characteristics investigated for first time using extended source/drain with high-k gate stack. The detailed analysis like transfer (ID-VGS), output (ID-VDS), drain induced barrier lowering (DIBL), subthreshold swi...

Amount of power consumption is one of the important measures of performance of an integrated circuit. CMOS is the latest technology which is in use till date. This paper gives an overview of the power dissipation occurring in CMOS circuit. The paper then describes the advantages and limitations of power optimization techniques of CMOS. As we go deeper into the nanometer scale, MOS transistors f...

In this paper we present a compact model of DoubleGate MOSFET architecture including ballistic and quasiballistic transport down to 20 nm channel length. In addition, this original model takes into account short channel effects (SCE/DIBL) by a simple analytical approach. The quasi-ballistic transport description is based on Lundstrom’s backscattering coefficient given by the socalled flux metho...

The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally demonstrated with a high mobility In0.53Ga0.47As channel and atomic-layer-deposited (ALD) Al2O3/WN gate stacks by a top-down approach. A wellcontrolled InGaAs nanowire release process and a novel ALD high-k/metal gate process has been developed to enable the fabrication of III-V GAA MOSFETs. Well-behaved on-state an...