In this paper, we assimilate and integrate two recent developments in prefix adder design and theory to create a fault-tolerant, real-time reconfigurable prefix adder. By exploiting the inherent redundancy of a Kogge-Stone adder we are able to extract signals to detect and correct from a single-fault. Our 16-bit design consumes less than 44% the hardware overhead of a comparable triple modular ...

Adders are of fundamental importance in a wide variety of digital systems. Many fast adders exist, but adding fast using low area and power is still challenging. This paper presents a new bit block structure that computes propagate signals called “carry strength” in a ripple fashion. Several new adders based on the new carry select Adder structure are proposed. Comparison with well-known conven...

over the past few decades, the intense growth of portable communication devices leads to stringent need of efficient system performance. The system performance is upgraded by reducing the computation time. The Residue Number System performs the computations fast and makes use of the power and energy efficiently. In this paper, the modified prefix adders are proposed to perform the fast modulo c...

In this paper a Split Radix FFT without the use of multiplier is designed. All the complex multiplications are done by using Distributed Arithmetic (DA) technique. For faster calculation parallel prefix adder is used. Basically high radix algorithms are developed for efficient calculation of FFT. These algorithms reduces overall arithmetic operations in FFT, but increases the number of operatio...

Flying-Adder frequency synthesis architecture is a comparatively new technique of generating fractional frequency derived from reference frequency. The first advantage is that system consists of pure digital circuits. The second advantage is fast response. On the other hand, this synthesizer generates a desired average frequency, which is not spectrally pure. Since its invention, it has been ut...

This brief presents a fast sign detection algorithm for the residue number system moduli set {2n+1 − 1, 2n − 1, 2n}. First, a sign detection algorithm for the restricted moduli set is described. The new algorithm allows for parallel implementation and consists exclusively of modulo 2n additions. Then, a sign detection unit for the moduli set {2n+1 − 1, 2n − 1, 2n} is proposed based on the new s...

– Because calculation models of arithmetic logic units based on many-sorted algebras have been proposed, we continue to verify the structure and design of these circuits using the Mizar proof checking system. To evaluate our formal veri cation method on a real production calculation circuit, we describe the formalization of the concept of the 4–2 compressor as a four-inputs–two-outputs binary a...

this paper presents a programmable digital finite impulse response (FIR) filter for low-power applications. A 10tap programmable FIR filter was implemented and fabricated in CMOS 0.25m technology based on the proposed architectural and circuit-level techniques. The chip‟s core contains approximately 130 K transistors and occupies 9.93 mm2 areas. The architecture is based on a computation sharin...

This paper explores the design of efficient test sets and test-pattern generators for on-line BIST. The target applications are high-performance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of carry-lookahead, most existing BIST methods are unsuitable for these applications. High-level models are used to identify potential test sets...