We like to introduce fQuantum, a Quantum Computing Fault Simulator and new quantum computing fault model based on Hadamard, PauliX, PauliY and PauliZ gates, and the traditional stuckat-1 SA1 and stuck-at-0 SA0 faults. We had close to 100% fault coverage on most circuits. The problem with lower coverage comes from function gates, which we will deal with, in future versions of this paper. Keyword...

Fault-tolerant design of analog circuits is more difficult than that of digital circuits. Abhijit Chatterjee has proposed a continuous checksum-based technique to design fault-tolerant linear analog circuits. However, some faults in the passive elements cannot be detected if the checker has not been designed appropriately. This paper addresses the fault coverage issue in the continuous checksum...

We propose a new statistical technique for estimating fault coverage in combinational circuits. Our method requires fault-free simulation of a random sample of vectors from the test vector set. Fault coverage is computed from controllabilities and observabilities both deened as probabilities and the method is applicable to any fault model like stuck-at-faults or delay faults. Experimental resul...

Due to imperfect fault coverage, the reliability of redundant systems cannot be enhanced unlimitedly with the increase of redundancy. Thus it is essential to study the optimal structure of redundant systems. This paper considers a multi-state series-parallel system with two types of parallelization: redundancy and work sharing. Different from existing works which consider single-fault coverage,...

Efficient methods to evaluate the quality of a test set in terms of its coverage of arbitrary defects in a circuit are presented. Our techniques rapidly estimate arbitrary defect coverage because they are independent of specific, physical, fault models. We overcome the potentially explosive computational requirements associated with considering all possible defects by implicitly evaluating mult...

In this paper, we employ the Communicating finite state machine (CFSM) model for networks to investigate fault management using passive testing. First, we introduce the concept of passive testing. Then, we introduce the CFSM model, the observer model and the fault model with necessary assumptions. We introduce the fault detection algorithm using passive testing. Then, we briefly present our new...

Sequential test generation becomes very time consuming when the circuit-under-test has many hard-to-test faults. This happens in cyclic sequential circuit. Design-for-testability method is applied on such circuit in order to speed up test generation time. However, this introduces huge area overhead. Alternatively, functional test generation is used to generate test sequences. In this option, st...

Microprocessor-based embedded systems are increasingly used to control safetycritical systems (e.g., air and railway traffic control, nuclear plant control, aircraft and car control). In this case, fault tolerance mechanisms are introduced at the hardware and software level. Debugging and verifying the correct design and implementation of these mechanisms ask for effective environments, and Fau...

We present a new probabilistic fault coverage model that is accurate, simple, predictive, and easily integrated with the normal design flow of built-in self-test circuits. The parameters of the model are determined by fitting the fault simulation data obtained on an initial segment of the random test. A cost-based analysis finds the point at which to stop fault simulation, determine the paramet...

We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by signiicantly reducing the number of injected faults and faulty-event evaluations. Speciically, we dynamically reduce injection of two types of faults: (1) hyperactive faults that never get detected, and (2) faults whose effects never propagate to a ip-op or primary ou...