The routing of integrated circuits is an important procedure of the physical design after the layout. For this reason, an improved Field Programmable Gate Array (FPGA) routing approach is proposed based on the ant colony optimization. Experimental results suggest that the proposed approach is feasible and correct.

The cavity control system for the TESLA TeV–Energy Superconducting Linear Accelerator project is initially introduced in this paper. The FPGA – Field Programmable Gate Array technology has been implemented for digital controller stabilizing cavity field gradient. The cavity SIMULINK model has been applied to test the hardware controller. The step operation method has been developed for testing ...

The current network technologies and market are pushing the envelope for high-performance computing power at the edge of the network. One such technology support for this computational power is the on-the-field reconfigurable technologies. In this paper we present an overview of a highly-parallel Field Programmable Gate Array (FPGA) system architecture called Super Reconfigurable Fabric Archite...

We propose a classification of high and low-level compiler optimizations to reduce the clock period, power consumption and area requirements in Field-programmable Gate Array (FPGA) architectures. The potential of each optimization, its effect on clock period, power and area and machine dependency is explained in detail.

In this work a temperature predictor has been designed. The prediction is made by an artificial neural network multilayer perceptron. Initially, the floating point algorithm was evaluated. Afterwards, the fixed point algorithm was designed on a Field Programmable Gate Array (FPGA). The architecture was fully parallelized and a maximum delay of 74 ns was obtained. The design tool used is System ...

The paper proposes a new fast Fourier transform (FFT) protection algorithm for digital relaying based on field-programmable gate array (FPGA), constructs detailed models and performs corresponding simulations. Simulation results show that the harmonic components of voltages and currents can be conveniently calculated, and the digital protection functions can be effectively fulfilled with enhanc...

The paper focuses on the design and implementation of the base-band basic receiving functions, for a binary CP-FSK demodulator pilot study, as independent modules of a complete Reconfigurable Data-Link (RDL). A model-based approach and Software Defined Radio (SDR) paradigm are used for the design. The implementation will be executed on Field-Programmable Gate Array (FPGA) based hardware.

This paper shows our work on performance optimized implementations of low-level vision algorithms on a Digital Signal Processor (DSP). The platform is a TI TMS320C6414 DSP running with 1 GHz and is therefore a cutting edge DSP. Performance optimization steps for DSP implementations are shown. A final benchmark compares the DSP with Field Programmable Gate Array (FPGA) implementations.

This paper proposed Mixed signal processor (MSP) based digital controllers are specifically optimized. The proposed single multiply-accumulate (MAC) architecture has implemented using field programmable gate array (FPGA) and design multi converter. A detailed description of flexible single multiplier accumulator processor architecture is given and comparison is made with an existing solution wi...

The Space Vector Pulse Width Modulation (SVPWM) is used for three phase bridge Inverter to produce AC output voltage of desired magnitude and frequency. The purpose of controller is to produce regulated output voltage with low distortion under varying load conditions. A triangular carrier based space vector pulse width modulation is developed in MATLAB using Xilinx block set and executed in Fie...