The present investigation was aimed to formulate and evaluate the gastro-retentive floating microballoons of glipizide using hydrophilic polymers hydroxypropyl methylcellulose (HPMC) and Eudragit RS100 (RS 100) by emulsion solvent evaporation technique. The floating microballoons were evaluated using micromeritic properties, buoyancy, in vitro drug release, scanning electron microscopy and stab...

Despite 9/11, “United We Stand,” and the USA Patriot Act, it seems that we are still afflicted by logocentrism and essentializing metanarratives. Decades of inoculation by deconstructive serums—first introduced by Jacques Derrida’s 1966 lecture at Johns Hopkins University entitled “Structure, Sign, and Play in the Discourse of the Human Sciences”—have failed to immunize us, readers and scholars...

The Satisfiability Modulo Theory (SMT) problem over floating-point arithmetic is a major hurdle in applying SMT techniques to real-world floatingpoint code. Solving floating-point constraints is challenging in part because floating-point semantics is difficult to specify or abstract. State-of-the-art SMT solvers still often run into difficulties when solving complex, non-linear floating-

We present algorithms that solve the following problem: given three ranges of floating-point numbers Rx, Ry , Rz , a floating-point operation (op), and a rounding-mode (round), generate three floating-point numbers x̄, ȳ, z̄ such that x̄ ∈ Rx, ȳ ∈ Ry , z̄ ∈ Rz , and z̄ = round(x̄ op ȳ). This problem, although quite simple when dealing with intervals of real numbers, is much more complex when consider...

We use reduced precision checking (RPC) to detect errors in floating point arithmetic. Prior work explored RPC for addition and multiplication. In this work, we extend RPC to a complete floating point unit (FPU), including division and square root, and we present precise analyses of the errors undetectable with RPC that show bounds that are smaller than prior work. We implement RPC for a comple...

OVERVIEW FPGAs are increasingly used as parallel processing engines for demanding digital signal processing applications. Benchmark results show that on highly parallelizable workloads, FPGAs can achieve higher performance and superior cost/performance compared to digital signal processors (DSPs) and general-purpose CPUs. However, to date, FPGAs have been used almost exclusively for fixed-point...

In this paper we present a design for a floating point unit partially compliant with the IEEE 754 floating point standard. The unit fully implements comparisons and partially implements floating-point addition and multiplication. It is fully parametrized and may be used with floating point numbers whose composite fields have widths of any desired length.