Latency-insensitive systems were recently proposed by Carloni et al. for the design of single-clock systems-on-a-chip (SoC’s) using predesigned IP blocks. The goal of this paper is to extend and generalize latency-insensitive systems in such a way that they can be applied to GALS architectures with multiple clocks. In particular, we propose two extensions. The first extension allows each synchr...

We used DNA microarrays to measure transcription and iTRAQ 2D liquid chromatography-mass spectrometry/mass spectrometry (a mass-tag labeling proteomic technique) to measure protein expression in 14 strains of Escherichia coli adapted for hundreds of generations to growth-limiting concentrations of either lactulose, methylgalactoside, or a 72:28 mixture of the two. The two ancestors, TD2 and TD1...

As explained in the companion paper by Thomas Villiger et. al. and in [1] a GALS system is partitioned into many Locally-Synchronous Islands, such as the one shown in Fig. 1. The GALS approach restricts the asynchronous parts to some well-known circuits contained in a Self-Timed Wrapper around each Synchronous Island and makes it possible to use the synchronous design paradigm for the Synchrono...

O uso de ferramentas ensino tornou-se uma alternativa para complementar a aprendizagem do conteúdo escolar. Este artigo faz panorâmica aspectos da Compilação e análise desempenho das computacionais GALS, Grammophone, The Context Grammar Free Checker, Verto Parsing Simulator que foram desenvolvidas suporte ao processo compilação têm como objetivo o apoio aprendizado disciplina Compiladores. Há v...

This report investigates the effectiveness of use of NoCs in the target hardware accelerator design and assesses the applicability of the NoC solution. The system planned to be GALSified is investigated in the scope of trade off between NoC implementation difficulties and benefits. An alternative hardware accelerator design that could benefit more from NoC implementation is discussed. Finally, ...

In this paper, we propose an asynchronous wrapper with new handshake circuits for the data communication in GALS systems. The handshake circuits include two data-ports and a local clock controller. we present two approaches for the implementation of dataports; one with pure standard cells and the other with Muller-C elements.The detailed design methodology is given and the circuits are validate...

Recently we proposed a mathematical framework offering diverse models of computation and a formal foundation for correct-byconstruction deployment of synchronous designs over distributed architecture (such as GALS or LTTA). In this paper, we extend our framework to model explicitly causality relations and scheduling constraints. We show how the formal results on the preservation of semantics ho...

In [12] we started a research on a distributed-timed extension of Petri nets where time parameters are associated with tokens and arcs carry constraints that qualify the age of tokens required for enabling. This formalism enables to model e.g. hardware architectures like GALS. We give a formal definition of process semantics for our model and investigate several properties of local versus globa...

The coupling of simultaneous switching noise through the substrate presents an important issue to integration of both noisy digital and sensitive analog circuitry in mixedsignal integrated circuits. Noise is generated by digital aggressor circuits, it further propagates through the common substrate, and finally impacts the performance of analog victim circuitry through body effect and capacitiv...