We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theor...

Two-dimensional electro-thermal simulations of GaN-based metal-semiconductor fieldeffect transistor are performed in the framework of the drift-diffusion model. The dependence of the hot spot temperature in transistors with many gates on the gate-to-gate pitch is studied. The case of SiC substrate is compared to the case of sapphire substrate. The ambient temperature effect on transistor perfor...

This paper presents a gate sizing method which formulates minimum active area solutions under delay constraints. It is based on the logical effort delay model. Such minimization of transistor widths has direct impact on the power consumption and circuit area reduction. The explicit formulation of the method takes into account the maximum input capacitance, the output load to be driven, and the ...

Low voltage (LV) analog circuit design techniques are addressed in this tutorial. In particular, (i) technology considerations; (ii) transistor model capable to provide performance and power tradeoffs; (iii) low voltage implementation techniques capable to reduce the power supply requirements, such as bulk-driven, floating-gate, and self-cascode MOSFETs; (iv) basic LV building blocks; (v) multi...

In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are gi...

We present a comprehensive review of product level reliability challenges for the 65nm technology node. The major reliability degradation mechanisms are analyzed for CMOS technologies. Historical data will show that hot carrier degradation has lost on importance and that negative bias temperature instability (NBTI) is the leading reliability concern for the 65nm technology node. Additionally, d...

The Screen-Grid Field Effect Transistor (SGrFET) is a planar MOSFET-type device with a gating configuration consisting of metal cylindrical fingers inside the channel perpendicular to the current flow. The SGrFET operates in a MESFET mode using oxide insulated gates. The multi-gate configuration offers advantages for both analog and digital applications, whilst the gate cylinder holes can be ex...

The gate dependence of a Coulomb attractive random telegraph signal is observed in a single-walled carbon nanotube field effect transistor for temperatures varying from 0.32 to 24 K. The mechanism of the Coulomb attractive random telegraph signal is attributed to the carrier tunneling between the carbon nanotube and the Coulomb attractive defect. The random telegraph signal is also studied unde...

Mobile computing devices like mobile, laptops& tablets that covered large market of end user facing battery issues is an open challenge for research scholars. In this project work I have attempt to optimize power [batteries relate issues] at decoding. Stare of most efficient error control LDPC code which is being used. In this work bit flipping decoder hard decision decoding is used which can b...

In this report, a parameter extraction procedure and a model presented in [4] are tested using a 280×0.25μm transistor manufactured in a 0.25 μmCMOS process. The extraction procedure is based on two sets of S-parameter measurements. The first transistor measurement is in the linear region, to obtain the extrinsic terminal resistances which are biasindependent . The intrinsic parameters of the t...