i ABSTRACT Reducing device dimensions, increasing transistor densities, and smaller timing windows, expose the vulnerability of processors to soft errors induced by charge carrying particles. Since these factors are inevitable in the advancement of processor technology, the industry has been forced to improve reliability on general purpose Chip Multiprocessors (CMPs). With the availability of i...

328 0740-7475/05/$20.00 © 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers THERE IS RENEWED INTEREST in using hardware redundancy to mask faulty behavior in nanoelectronic components. In this article, we go back to the early ideas of von Neumann and review the key concepts behind Ntuple modular redundancy (NMR), hardware multiplexing, and interwoven redunda...

One of the primary concerns in any system design problem is to prepare a highly reliable system with minimum cost. One way to increase the reliability of systems is to use redundancy in different forms such as active or standby. In this paper, a new nonlinear multi- objective integer programming model with the choice of redundancy strategy and component type is developed where standby strategy ...

This paper presents EME, a low-cost solution for a highly modular multiprocessing hardware-software environment useful in designing autonomous mobile robots. High processing capabilities, the ability to interface a large number of sensors and actuators, extensibility, redundancy and exibility are issues addressed by this environment. An autonomous robot equipped with two cameras, one for line-f...

Almost all artificial neural networks are by default fully connected, which often implies a high redundancy and complexity. Little research has been devoted to the study of partially connected neural networks, despite its potential advantages like reduced training and recall time, improved generalization capabilities, reduced hardware requirements, as well as being a step closer to biological r...

Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate two systematic approaches to low-cost, low-latenc...

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The interest for real three dimensional displays has been revived over the past few years, and the high resolution images that capturing and reproducing of 3D imagery demands, must be addressed with an efficient compression scheme. An area-efficient hardware implementation of a real-time disparity estimation scheme targeted to Integral Photography 3D images is presented, exploiting the inherent...

This report is an introduction to fault-tolerance concepts and systems, mainly from the hardware point of view. An introduction to the terminology is given, and different ways of achieving fault-tolerance with redundancy is studied. Knowledge of software fault-tolerance is important, so an introduction to software fault-tolerance is also given. Finally, some systems are studied as case examples...

This paper discusses the issue of providing tolerance to both hardware and software faults by defining several hybrid-fault-tolerant architectures, which can co-exist and work simultaneously at the top of the supporting environment, and introduces a systematic method for evaluating their dependability, efficiency and response time. To address general-purpose distributed systems where multiple u...