This paper is a blueprint for the use of a massively parallel SIMD computer architecture for the simulation of various forms of computer arithmetic. The particular system used is a DEC/MasPar MP-1 with 4096 processors in a square array. This architecture has many advantages for such simulations due largely to the simplicity of the individual processors. Arithmetic operations can be spread acros...

Most of the signal processing algorithms using floating point arithmetic, which requires millions of operations per second to be performed. For such stringent requirement design of fast, precise and efficient circuit is needed. This article present an IEEE 754 floating point unit using carry look ahead adder and radix-4 modified Booth encoder multiplier algorithm and the design is compared in t...

This paper primarily deals with the construction of arithmetic Logic Unit (ALU) using Hardware Description Language (HDL) using Xilinx Vivado 14.7 and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. ALU of digital computers is an aspect of logic design with the objective of developing appropriate algorithms in order to achieve an efficient utilization ...

Unities in the processes involved in solving arithmetic problems of varying operations have been suggested by studies that have used both factor-analytic and information-processing methods. We designed the present study to investigate the convergence of mental processes assessed by paper-and-pencil measures defining the Numerical Facility factor and component processes for cognitive arithmetic ...

The challenge in designing a floating-point arithmetic co-processor/processor for scientific and engineering applications is to improve the performance, efficiency, and computational accuracy of the arithmetic unit. The arithmetic unit should efficiently support several mathematical functions corresponding to scientific and engineering computation demands. Moreover, the computations should be p...

In this paper, an area-efficient implementation of a fast converging square root algorithm is presented. The design of special arithmetic operations differs in many ways from the traditional tasks that digital designers are used to, and the role of parameterizibility and mapping of mathematical algorithms into digital hardware is discussed. Certain realworld applications requiring the use of th...

Ten years ago IEEE standard 1] for oating-point arithmetic became oocial. Each IEEE oating-point format supports: its own set of nite real numbers, 1, two distinguished values +0 and ?0 and a set of special values called NaNs (Not-a-Number). Arithmetic operations include operations on numeric, non-numeric or mixed operands in four rounding modes. A number of exceptional situations may arise dur...