It is introduced a new genetic algorithm to synthesize the negative-type second generation current conveyor (CCII-) by superimposing a voltage follower (VF) with a current follower (CF). First, the VF and CF are described by binary genes. Second, the gene CF is inverted, rigth-shifted and multiplied (AND operation) with the gene VF to verify that both genes can be superimposed to synthesize the...

Bias temperature instability (among other problems) is a key reliability issue with nanoscale CMOS transistors. Especially in sensitive circuits such as sense amplifiers of SRAM arrays, transistor aging may significantly increase the probability of failure. By analyzing the Current Based Sense Amplifier circuit and Voltage-Latched Sense Amplifier circuit through HSPICE simulations, we observe t...

This paper presents the design of a low power second-order continuous-time sigma-delta modulator for low power applications. The loop filter of this modulator has been implemented based on the nonlinear transconductance-capacitor (Gm-C) by employing current-mode technique. The nonlinear transconductance uses floating gate MOS (FG-MOS) transistors that operate in weak inversion region. The propo...

This paper examine the effect of subthreshold voltage in function, delay, power and energy. Benchmark circuit c6288 in 45 nm technology is used in this design. The focus of this work is to find the optimal power delay product of benchmark circuit at subthreshold operation. The simulation was done using HSPICE. Results show that the 45nm cell libraries support the subthreshold operation of elect...

In this paper, we propose a S/H circuit with the clock boost technique and the input signal tracking technique. The proposed circuit generates the clock with the amplitude of VDD + vin, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintainng low distortion. Furthermore, the hold error caused by the char...

In this paper, a new logiedesign style called Pseudo Dynamic Logic (SDL) is introduced. In this logiedesign style, the internal nodes of the logic circuits are not precharged to high or low values, rather the initial charges on nodes are shared to yield an intermediate precharge value for faster evaluation. A 32-bit adder has been designed and simulated using HSPICE Level-49 parameters of a 0 ....

A new voltage-programmed pixel circuit using soluble-processed organic thin film transistors (OTFTs) for an active matrix organic light emitting diode (AMOLED) is proposed. The proposed circuit is composed of four switching TFTs, one driving TFT and one storage capacitor, which is simulated by HSPICE. The proposed circuit can compensate for the non-uniformity of OLED current caused by the thres...

Sangjin Hong, Suhwan Kim, Marios C. Papaefthymiou, and Wayne E. Stark Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, MI 48109 USA Abstra t—Large fixed-throughput fast Fourier transform (FFT) modules are used in multi-carrier spread spectrum receiver design for demodulation and synchronization. The power dissipation of an FFT module depends highly on ...

This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier. The design procedure focuses on the noise performance, which is the key requirement for low noise operational amplifiers. Based on the noise level and other specifications such as bandwidth, signal swing, slew rate, and power consumption, the device sizes and the biasing con...

A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35μm standard CMOS technology. DC gain achieved is 56.7dB an...