CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-lm CMOS technology to achieve 1-kV CDM ESD robustness. 2007 Elsevier Ltd. All rights reserved.

Q1 Laser fault injection has been proved to be a useful tool for attacks on integrated circuits. Transistors hit by a pulse of photons causes them to conduct transiently, thereby introducing transient logic errors, such as register value modifications, memory dumping, and so on. Attackers can make use of this abnormal behavior and extract sensitive information that the devices try to protect. T...

The problem of single channel speaker separation, attempts to extract a speech signal uttered by the speaker of interest from a signal containing a mixture of auditory signals. Most algorithms that deal with this problem, are based on masking, where reliable components from the mixed signal spectrogram are inversed to obtain the speech signal from speaker of interest. As of now, most techniques...

This paper uses a CAD methodology proposed by the authors to design a low-power 2ndorder Σ∆M. This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy metering mixed-signal ASIC and features 16.4bit at a digital output rate of 9.6kHz with a power consumption of 1.71mW. It yields a value of the figure which is the smallest reported to now, thus demon...

This paper describes the integration of analog, digital, and mixed-signal IC design in the undergraduate ECE curriculum at Lafayette College. This integration is being accomplished by adding IC design coverage to the required electronics sequence and including analog and mixed-signal coverage in a what was previously an “alldigital” VLSI Design elective. As a result, all ECE students at Lafayet...

There is currently a huge gap between the two main technologies used to implement custom digital integrated circuit (IC) designs. At one end of the spectrum are field programmable gate arrays (FPGAs). These devices have relatively low design costs and short design times, but they also have high per-unit costs and are limited in terms of design size, complexity, and performance. At the other end...

The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stage can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses...

Bonding wires are extensively used in integrated circuit (IC) packaging and circuit design in RF applications. An approach to fast three-dimensional (3-D) modeling of the geometry for bonding wires in RF circuits and packages is demonstrated. The geometry can readily be used to extract electrical parameters such as inductance and capacitance. An equivalent circuit is presented to model the freq...

Piezoelectric materials constitute a class of intelligent materials that are helpful for monitoring the structural integrity. The principle of the piezoelectric impedance-based structural health monitoring technique is to measure the electrical impedance of a piezoelectric patch attached to a structure in a certain frequency range. Electrical impedance variations indicate physical changes in th...