NULL Convention Logic (NCL) provides an asynchronous design methodology employing dual-rail signals, quad-rail signals, or other Mutually Exclusive Assertion Groups (MEAGs) to incorporate data and control information into one mixed path. In NCL, the control is inherently present with each datum, so there is no need for worsecase delay analysis and control path delay matching. This dissertation ...

This paper presents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13 μm CMOS technology. The simulation results demonstrate a linear input-output characteristic ...

Nowadays there are different kinds of attacks on Field Programmable Gate Array (FPGA). As FPGAs are used in many different applications, its security becomes an important concern, especially in Internet of Things (IoT) applications. Hardware Trojan Horse (HTH) insertion is one of the major security threats that can be implemented in unused space of the FPGA. This unused space is unavoidable to ...

In this paper, we consider the use of a limited pipelining scheme in conjunction with a gate resizing technique to improve the optimal clock speed of a combinational logic block. Gate resizing is restricted to a small subset of the circuit, and target gates are identiied using a delay sensitivity metric introduced here. 1 Abstract In this paper, we consider the use of a limited pipelining schem...

This paper presents an area-time-efficient systolic structure for multiplication over GF (2 m ) based on irreducible all-one polynomial (AOP). We have used a novel cut-set retiming to reduce the duration of the criticalpath to one XOR gate delay. It is further shown that the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic bra...

Aggressive downscaling of CMOS devices in every technology generation resulted in higher integration density and performance. At the same time, yield, which is the ratio of flawless versus all fabricated chips, drastically decreased. Failed chips are divided in defect devices (defect yield) and devices, which failed the desired performance (parametric yield). Parameter variations, which strongl...

This paper presents strategies to insert bu ers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeo s. The delay model incorporates placement-based information and the e ect of input slew rates on gate delays. The results obtained by using the new method are signi cantly better than the results given by merely using a TILOS-like transistor sizing algorit...

The probabilistic methods for power estimation in combinational circuits are classified in two categories according to the adopted gate-delay model. The zero and real gate-delay power estimation methods. Under zero delay model, assuming spatiotemporal independence among the circuit signals, the switching activity, E(sw), of a circuit node, x, is given by ) 1 ( 2 2 ) ( 1 1 0 1 x x x x p p p p sw...

Both long and short path delays are used to determine the valid clocking for various CMOS circuits such as single phase latching, asynchronous, and wave pipelining. Therefore, accurate estimation of both long and short path delays is very crucial in the designing and testing of high speed CMOS circuits. Most of the previous approaches in detecting long and short sensitizable paths assume that t...