Today, and especially with the growing interest in distributed renewable energy sources (DRESs), modern electric power systems are becoming more complex. In order to increase DRES penetration, grid side converter (GSC) control techniques require appropriate synchronization algorithms that able detect voltage status as fast accurately possible. The drawbacks of published phase-locked loop (PLL) ...

This paper revisits the design of current controller for grid-connected voltage-source converters (VSCs), considering dynamic impacts phase-locked loop (PLL), weak grids, and voltage feedforward (VFF) control. First, a single-input single-output transfer-function-based model is proposed to characterize interactions control loops. It analytically found that proportional gain essentially aggravat...

This article addresses the issue of when to suppress or not to suppress the transmitted carrier in designing a coherent communication system employing a carrier tracking loop for carrier synchronization. Assuming that a phase-locked loop (PLL) is used whenever there exists a residual carrier and a Costas loop is used whenever the carrier is suppressed, the regions of system parameters that deli...

Out of various moving average filter (MAF)-based phase-locked-loop (PLL), quasi type-1 PLL (QT1-PLL) is widely adopted due to its fast dynamic performance, implementation simplicity, and harmonics rejection abilities. However, the performance QT1-PLL deteriorates in presence an off-nominal frequency unbalanced grid voltage component. Moreover, sensitivity towards fundamental negative sequence (...

This paper offers a detailed analysis as well tuning and discretization approach of the presented frequency-fixed dual second order generalized integrator based phase-locked loop (FFDSOGI-PLL) for three-phase power systems. The method combines different single- PLL approaches by ensuring high phase- frequency tracking properties. comparison with standard frequency-variable DSOGI-PLL three recen...

A third order Phase locked loop, PLL, is widely used in communication systems. Lately, researcher had found that under certain conditions, such as gain, PLL is experiencing chaotic oscillations. For a single PLL, studies have shown that when the gain of PLL increases, it will encounter a chaotic behavior. To see the mutual effect of two coupled PLL, this paper will derive the mathematical dynam...

-A PLL is a closed loop system that locks the phase of an output signal to an input reference signal. The term “lock” refers to a constant or zero phase difference between two signals. The components of PLL are the Phase Frequency Detector (PFD), the charge pump (CP), the low pass filter (LPF), and the voltage controlled oscillator (VCO). In which the charge pump has been modified in order to o...

This paper presents a novel phase-locked loop (PLL) structure for improving the transient stability of grid-connected converters by introducing voltage normalization control (VNC) in conventional PLL. First, underlying mechanism losing synchronization during grid fault is analyzed, and it revealed that key factor significant decrease magnitude at point common coupling (PCC). In order to avoid d...

This paper deals with different approaches to design Phase Locked Loop (PLL) frequency synthesizer. PLL system responds to both frequency and phase of the input signals, automatically raising or lowering the frequency of controlled oscillator until it is matched to the reference in both frequency and phase. The performance of PLL frequency synthesizer is improved by using different Voltage cont...

An ASIC design of Dual Edge Triggered Phase Detector(DET PD) for Delay locked loop(DLL) and Phase locked loop(PLL) applications is proposed in this paper.The proposed DET PD has high locking speed and less jitter. The designs are based on TSPC flip flop logic, which overcomes the issue of narrow capture range. The Double edge triggered phase detector dissipates less power than conventional desi...