In this paper, we propose a simple practical scheme for many-to-many IP multicasting. The proposed scheme is based on the core based tree (CBT) protocol, and designed to enhance the CBT in the viewpoints of tree cost and trafic concentration. In the scheme, each group user is simply connected to the nearest core router in the network. Each core router forwards the source traffic to networks via...

Shared memory many-core processors such as GPUs have been extensively used in accelerating computation-intensive algorithms and applications. When porting existing algorithms from sequential or other parallel architecture models to shared memory many-core architectures, non-trivial modifications are often needed in order to match the execution patterns of the target algorithms with the characte...

Nowadays, multi-core architectures become popular for embedded systems. As VLSI technology is scaling to deep sub-micron domain, an envisioned trend is that the architectures of embedded systems are moving from multiple cores to many cores. Although state-of-art multicore and future many-core architectures provide enormous potential, scaling the number of computing cores does not directly trans...

OF THE DISSERTATION Optimizing Many-Threads-to-Many-Cores Mapping in Parallel Electronic System Level Simulation By Guantao Liu Doctor of Philosophy in Computer Engineering University of California, Irvine, 2017 Professor Rainer Dömer, Chair In hardware/software codesign, Discrete Event Simulation (DES) has been in use for decades to verify and validate the functionality of Electronic System Le...

S-NET is a declarative coordination language and component technology primarily aimed at modern multicore/many-core chip architectures. It builds on the concept of stream processing to structure dynamically evolving networks of communicating asynchronous components, which themselves are implemented using a conventional language suitable for the application domain. We sketch out the design and i...

The continuous improvements offered by the silicon technology enables the integration of always increasing number of cores on a single chip. Following this trend, it is expected to approach microprocessor architectures composed of thousands of cores (i.e., kilo-core architectures) in the next future. To cope with the increasing demand for high performance systems, many-core designs rely on inte...

cognitive architectures (cas) are the core of artificial cognitive systems. a ca is supposed to specify the human brain at a level of abstraction suitable for explaining how it achieves the functions of the mind. over the years a number of distinct cas have been proposed by different authors and their limitations and potentials were investigated. these cas are usually classified as symbolic and...

The continuous improvements offered by the silicon technology make possible the integration of always increasing number of cores on a single chip. Following this trend, it is expected to approach microprocessor architectures composed of thousands of cores (i.e., kilo-core architectures) in the next future. To cope with the increasing demand for high performance systems, many-core designs rely o...

Cognitive Architectures (CAs) are the core of artificial cognitive systems. A CA is supposed to specify the human brain at a level of abstraction suitable for explaining how it achieves the functions of the mind. Over the years a number of distinct CAs have been proposed by different authors and their limitations and potentials were investigated. These CAs are usually classified as symbolic and...