This paper describes a three-dimensional DRAM in which the floating body capacitance (FBC) of a fully depleted SOI (FD-SOI) device is used as a storage node. This 1T DRAM lends itself particularly well to a 3D waferto-wafer bonding process because of the absence of deep etched and filled trench capacitor structure, and the improved thickness control tolerance in wafer thinning. A novel three-ti...

DAC (Digital to Analog Converter) is the enabling inverse technology of ADC that generates analog output proportionate to given digital input. In most of the control and digital processing system requires the DAC for meddlesome with real world. But most of the digital controlling microprocessor and microcontroller don’t have an on chip DAC integrated peripheral architecture. For such implementi...

By the end of the decade, as VLSI integration levels continue to increase, building a multiprocessor system on a single chip will become feasible. In this paper, we propose to analyze the tradeoos involved in designing such a chip, and speciically address whether to allocate available chip area to larger caches or to large numbers of processors. Using the dimensions of the Alpha 21064 microproc...

The Altera EPXA10DB is a development platform for reconfigurable computing, coupling an ARM microprocessor and a modest Altera Programmable Logic Device (PLD) on the same chip. Streams-C is a "C" style language that addresses hardware and software generation by extending the C language. A new port of Streams-C for the EPXA10DB is being developed to provide a standalone, custom-hardware-accelera...

Structural testing with both scan test and Built-in Self-Test (BIST) has proven effective for detecting both gross static and at-speed defects. As tools and techniques improve, structural testing is approaching the high level of test quality necessary to eliminate test escapes. However, scan and BIST do not accomplish all that is needed. Parametric and functional tests are still needed for adva...

The IBM POWER4 is a new microprocessor organized in a system structure that includes new technology to form systems. The name POWER4 as used in this context refers not only to a chip, but also to the structure used to interconnect chips to form systems. In this paper we describe the processor microarchitecture as well as the interconnection architecture employed to form systems up to a 32-way s...

This paper introduces a multi-parameter measurement system, which is used for recording the temperature and humidity, atmospheric pressure, rotation speed and acceleration, etc. The system uses a 32-bit RISC microprocessor of STM32F103ZET6 based on the core of ARM Coretex-M3 as master chip. Meanwhile, it writes the data recorded to NAND FLASH. After it is over, it copies the data to host-comput...

The newly introduced Microprocessor Architecture for Java Computing (MAJC) supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruction level parallelism via a very long instruction word architecture (VLIW) and SIMD. The rst implementation, MAJC-5200, includes some key features of MAJC to realize a high performance multimedia processor. Two CPUs r...

The MC68030 is a virtual memory microprocessor based on an MC68020 core with additional enhanced performance features. Increased internal parallelism is provided by multiple internal data buses and address buses, and a versatile bus controller that supports synchronous burst cycle accesses in order to maximize performance with paged mode, nibble mode, and static column DRAM technology, or even ...

The traditional heterogeneous data transmission system of industrial enterprises has poor performance. In order to solve this problem, the design based on fuzzy algorithm is proposed. hardware composed STM32F107RCt6 microprocessor, FLASH memory, AS32-TTL-100 wireless module and DP83848x chip, which realizes two node functions. software introduces realize function, including source management mo...