Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial multipliers obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial multipliers is present...

By selecting the largest possible value of k ∈ (n/2, 2n/3], we further reduce the AND and XOR gate complexities of the CRT-based hybrid parallel GF (2) polynomial basis multipliers for the irreducible trinomial f = u + u + 1 over GF (2): they are always less than those of the current fastest parallel multipliers – quadratic multipliers, i.e., n AND gates and n− 1 XOR gates. Our experimental res...

We prove that standard Gaussian random multipliers are expected to stabilize numerically both Gaussian elimination with no pivoting and block Gaussian elimination. Our tests show similar results where we applied circulant random multipliers instead of Gaussian ones.

Based on fast finite-impulse response (FIR) algorithms (FFAs), this paper proposes new parallel FIR filter structures, which are beneficial to symmetric coefficients in terms of the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. The proposed parallel FIR structures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers ...

Systems subjected to holonomic constraints follow quite complicated dynamics that could not be described easily with Hamiltonian or Lagrangian dynamics. The influence of holonomic constraints in equations of motions is taken into account by using Lagrange multipliers. Finding the value of the Lagrange multipliers allows to compute the forces induced by the constraints and therefore, to integrat...

To estimate multipliers linking surveillance of salmonellosis, campylobacteriosis, and Shiga toxin-producing Escherichia coli (STEC) infections to community incidence, we used data from a gastroenteritis survey and other sources. Multipliers for severe (bloody stool/long duration) and milder cases were estimated from the component probabilities of doctor visit, stool test, sensitivity of labora...

This paper is devoted to the study of number representations and algorithms leading to efficient implementations of modular adders and multipliers on recent Field Programmable Arrays. Our hardware operators take advantage of the building blocks available in such devices: carrypropagate adders, memory blocks, and sometimes embedded multipliers. The first part of the paper describes three basic m...

This paper introduces the concept of Bessel multipliers. These operators are defined by a fixed multiplication pattern, which is inserted between the analysis and synthesis operators. The proposed concept unifies the approach used for Gabor multipliers for arbitrary analysis/synthesis systems, which form Bessel sequences, like wavelet or irregular Gabor frames. The basic properties of this clas...

High performance systems such as microprocessors, digital signal processors, filters, ALU etc. which is need of hour now days requires a lot of components. One of main component of these high performance systems is multiplier. Most of the DSP computations involve the use of multiply-accumulate operations, and therefore the design of fast and efficient multipliers is imperative. However, area an...

Recent computing-oriented FPGAs feature DSP blocks including small embedded multipliers. A large integer multiplier, for instance for a double-precision floatingpoint multiplier, consumes many of these DSP blocks. This article studies three non-standard implementation techniques of large multipliers: the Karatsuba-Ofman algorithm, non-standard multiplier tiling, and specialized squarers. They a...