The idea of using on chip packet switched networks for interconnecting a large number of IP cores is very practical for designing complex SoCs since it gives possibility of not only reusing IP cores but also the interconnection infrastructure. However, the real effort and time in using these Networks on Chip (NoC) goes in developing interfaces for connecting cores to the on-chip network. Standa...

Network on Chip (NoC) has emerged as a promising interconnection paradigm for complex on-chip communications. As fabrication cost is high, model based design of NoC and early exploration to make proper design decisions are important challenges in NoCs. To tackle these challenges, we use formal methods and utilize their expressivity and flexibility to model different behaviors of a NoC and their...

Advanced CMOS technology possibilities, power, communication and flexibility issues as well as the design gap are directing System-on-Chip (SoC) platforms towards Network-on-Chip (NoC) interconnected identical processing tiles (PT) such as the Montium processor [1]. It is broadly acknowledged that advanced technologies below 45nm come with significant yield and reliability problems, necessitati...

MPSoCs are today frequently designed as the composition of multiple voltage/frequency islands, thus calling for a GALS clocking style. In this context, the on-chip interconnection network can be either inferred as a single and independent clock domain or it can be distributed among core’s domains. This paper targets the former scenario, since it results in the homogeneous speed of the NoC switc...

The Network-on-Chip (NoC) approach for designing (System-on-Chip) SoCs is currently used for overcoming the scalability and efficiency problems of traditional on-chip interconnection schemes, such as shared buses and point-to-point links. NoC design draws on concepts from computer networks to interconnect Intellectual Property (IP) cores in a structured and scalable way, promoting design re-use...

The widespread adoption of MPSoCs (Multiprocessor System-on-Chip) in critical systems, turns security into an important design requirement. MPSoCs are able to support multiple applications on the same chip. The challenge is to provide a trustworthy MPSoC and guarantee that performance and security requirements of all the applications are met. Our work implements the QoSS (Quality-of-Security-Se...

With the continuous technology scaling, System On Chips (SoCs) have evolved considerably and can integrate an important number of Intellectual Property (IP) cores in the same chip. However, global interconnects are become the main performance limitation of SoCs. The Network on Chip (NoC) paradigm has emerged as an efficient interconnection structure addressing the global wire delay problem. Thi...

increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. nocs have features such as scalability and high performance. nocs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made noc. due to increasing number of cores, the placement of the cores i...

To alleviate the complex communication problems arising in the network-on-chip (NoC) architectures as the number of on-chip components increases, several novel interconnect infrastructures have been recently proposed to replace the traditional on-chip interconnection systems that are reaching their limits in terms of performance, power and area constraints. Wireless NoC (WiNoC) is among the mos...

The suggested new approach based on B-Event formal technics consists of suggesting aspects and constraints related to the reliability of NoC (Network-On-chip) and the over-cost related to the solutions of tolerances on the faults: a design of NoC tolerating on the faults for SoC (System-on-Chip) containing configurable technology FPGA (Field Programmable Gates Array), by extracting the properti...